APPENDIX D MC68000 INSTRUCTION EXECUTION TIMES
D.1 Introduction
This Appendix contains listings of the instruction execution times in terms of external clock (CLK) periods. In this data, it Is assumed that both memory read and write cycle times are four clock periods. A longer memory cycle will cause the generation of wait states which must be added to the total instruction time.
The number of bus read and write cycles for each Instruction is also included with the timing data. This data is enclosed in parenthesis following the number of clock periods and is shown as: (r/w) where r is the number of read cycles and w is the number of write cycles included in the clock period number. Recalling that either a read or write cycle requires four clock ...
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