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Microprocessors and Microcomputer-Based System Design, 2nd Edition

Name: Microprocessors and Microcomputer-Based System Design, 2nd Edition
Author: Mohamed Rafiquzzaman
ISBN: 9781000141467

by Mohamed Rafiquzzaman

November 2021

Intermediate to advanced

672 pages

25h 6m

English

CRC Press

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Cover
Title Page
Copyright Page
Preface
The Author
Dedication
Table of Contents
Chapter 1 Introduction to Microprocessors and Microcomputer-Based Applications
1.1 Evolution of the Microprocessor1.2 Microprocessor Data Types1.2.1 Unsigned and Signed Binary Integers1.2.2 BCD (Binary Coded Decimal) Numbers1.2.3 ASCII1.2.4 Floating-Point Numbers1.3 Microcomputer Hardware1.3.1 The System Bus1.3.2 The Microprocessor1.3.3 Memory Organization1.3.3.a Introduction1.3.3.b Main Memory Array Design1.3.3.c Memory Management Concepts1.3.3.d Cache Memory Organization1.3.4 Input/Output (I/O)1.3.4.a Programmed I/O1.3.4.b Standard I/O Versus Memory-Mapped I/O1.3.4.c Unconditional and Conditional Programmed I/O1.3.4.d Typical Microcomputer Output Circuit1.3.4.e Interrupt Driven I/O1.3.4.f Direct Memory Access (DMA)1.3.4.g Summary of Microcomputer I/O Methods1.3.4.h Coprocessors1.4 Microcomputer System Software and Programming Concepts1.4.1 System Software1.4.2 Programming Concepts1.4.2.a Assembly Language Programming1.4.2.b High-Level Language Programming1.4.2.c Which Programming Language to Choose?1.5 Typical Microcomputer Addressing Modes and Instructions1.5.1 Introduction1.5.2 Addressing Modes1.5.3 Instruction Types1.6 Basic Features of Microcomputer Development Systems1.7 System Development Flowchart1.7.1 Software Development1.7.2 Hardware Development1.8 Typical Microprocessors1.9 Typical Practical Applications1.9.1 Personal Workstations1.9.2 Fault-Tolerant Systems1.9.3 Real-Time Controllers1.9.4 Robotics1.9.5 Embedded Control
Chapter 2 Intel
2.1 Introduction2.2 Register Architecture2.3 Memory Addressing2.4 8085 Addressing Modes2.5 8085 Instruction Set2.6 Timing Methods2.7 8085 Pins and Signals2.8 8085 Instruction Timing and Execution2.8.1 Basic System Timing2.8.2 8085 Memory READ (IO/M = 0, RD = 0) and I/O READ (IO/M = 1, RD =_0)2.8.3 8085 Memory WRITE (IO/M = 0, WR = 0) and I/O WRITE (IO/M = 1, WR = 0)2.9 8085 Input/Output (I/O)2.9.1 8085 Programmed I/O2.9.1.a 8355/8755 I/O Ports2.9.1.b 8155/8156 I/O Ports2.9.2 8085 Interrupt System2.9.3 8085 DMA2.9.4 8085 SID and SOD Lines2.10 8085-Based System DesignQuestions and Problems
Chapter 3 Intel 8086
3.1 Introduction3.2 8086 Architecture3.3 8086 Addressing Modes3.3.1 Addressing Modes for Accessing Immediate and Register Data (Register and Immediate Modes)3.3.1.a Register Addressing Mode3.3.1.b Immediate Addressing Mode3.3.2 Addressing Modes for Accessing Data in Memory (Memory Modes)3.3.2.a Direct Addressing Mode3.3.2.b Register Indirect Addressing Mode3.3.2.c Based Addressing Mode3.3.2.d Indexed Addressing Mode3.3.2.e Based Indexed Addressing Mode3.3.2.f String Addressing Mode3.3.3 Addressing Modes for Accessing I/O Ports (I/O Modes)3.3.4 Relative Addressing Mode3.3.5 Implied Addressing Mode3.4 8086 Instruction Set3.5 8086 Assembler-Dependent Instructions3.6 ASM-86 Assembler Directives3.6.1 SEGMENT and ENDS Directives3.6.2 Assume Directive3.6.3 DUP Directive

3.7 System Design Using the 8086
3.7.1 Pins and Signals3.7.2 8086 Basic System Concepts3.7.2.a 8086 Bus Cycle3.7.2.b 8086 Address and Data Bus Concepts3.7.3 Interfacing with Memories3.7.3.a ROM and EPROM3.7.3.b Static RAMs3.7.3.c Dynamic RAMs3.7.4 8086 Programmed I/O3.8 8086-Based Microcomputer3.9 8086 Interrupt System3.9.1 Predefined Interrupts (0 to 4)3.9.2 User-Defined Software Interrupts3.9.3 User-Defined Hardware (Maskable Interrupts, Type Codes 3210 — 25510)3.10 8086 DMAQuestions and Problems
Chapter 4 Intel 80186/80286/80386
4.1 Intel 80186 and 802864.1.1 Intel 801864.1.2 Intel 802864.1.2.a 80286 Memory Management4.1.2.b Protection4.1.2.c 80286 Exceptions4.2 Intel 803864.2.1 Basic 80386 Programming Model
4.2.1.a Memory Organization and Segmentation
4.2.1.b Data Types4.2.1.c 80386 Registers4.2.1.d 80386 Addressing Modes4.2.2 80386 Instruction Set4.2.2.a Arithmetic Instructions4.2.2.b Bit Manipulation Instructions4.2.2.c Byte-Set-On Condition Instructions4.2.2.d Conditional Jumps and Loops4.2.2.e Data Transfer4.2.2.f Flag Control4.2.2.g Logical4.2.2.h String4.2.2.i Table Look-Up Translation Instruction4.2.2.j High-Level Language Instructions4.2.3 Memory Organization4.2.4 I/O Space4.2.5 80386 Interrupts4.2.6 80386 Reset and Initialization4.2.7 Testability4.2.8 Debugging4.2.9 80386 Pins and Signals4.2.10 80386 Bus Transfer Technique4.2.11 80386 Read and Write Cycles4.2.12 80386 Modes4.2.12.a 80386 Real Mode4.2.12.b Protected Mode4.2.12.c Virtual 8086 Mode4.3 80386 System Design4.3.1 80386 Memory Interface4.3.2 80386 I/O4.4 Coprocessor Interface4.4.1 Coprocessor Hardware Concepts4.4.2 Coprocessor Registers4.4.3 80387 InstructionsQuestions and Problems
Chapter 5 Motorola MC68000
5.1 Introduction5.2 68000 Programming Model5.3 68000 Addressing Structure5.4 68000 Addressing Modes5.4.1 Register Direct Addressing5.4.2 Address Register Indirect Addressing5.4.3 Absolute Addressing5.4.4 Program Counter Relative Addressing5.4.5 Immediate Data Addressing Mode5.4.6 Implied Addressing
5.5 68000 Instruction Set
5.5.1 Data Movement Instructions5.5.1.a MOVE Instructions5.5.1.b EXG and SWAP Instructions5.5.1.c LEA and PEA Instructions5.5.1.d LINK and UNLK Instructions5.5.2 Arithmetic Instructions5.5.2.a Addition and Subtraction Instructions5.5.2.b Multiplication and Division Instructions5.5.2.c Compare, Clear, and Negate Instructions5.5.2.d Extended Arithmetic Instructions5.5.2.e Test Instructions5.5.2.f Test and Set Instruction5.5.3 Logical Instructions5.5.4 Shift and Rotate Instructions5.5.5 Bit Manipulation Instructions5.5.6 Binary-Coded Decimal Instructions5.5.7 Program Control Instructions5.5.8 System Control Instructions5.6 68000 Stacks5.7 68000 Pins and Signals5.7.1 Synchronous and Asynchronous Control Lines5.7.2 System Control Lines5.7.3 Interrupt Control Lines5.7.4 DMA Control Lines5.7.5 Status Lines
5.8 68000 System Diagram
5.9 Timing Diagrams5.10 68000 Memory Interface5.11 68000 Programmed I/O5.11.1 68000-68230 Interface5.11.2 Motorola 68000-6821 Interface5.12 68000/2716/6116/6821-Based Microcomputer5.13 68000 Interrupt I/O5.13.1 External Interrupts5.13.2 Internal Interrupts5.13.3 68000 Exception Map5.13.4 68000 Interrupt Address Vector5.13.5 An Example of Autovector and Nonautovector Interrupts5.14 68000 DMA5.15 68000 Exception Handling5.16 Multiprocessing with the 68000 Using the TAS Instruction and AS (Address Strobe) SignalQuestions and Problems
Chapter 6 Motorola MC68020
6.1 Introduction6.2 Programming Model6.3 Data Types, Organization, and CPU Space Cycle6.4 MC68020 Addressing Modes6.4.1 Address Register Indirect (ARI) with Index and 8-Bit Displacement6.4.2 ARI with Index (Base Displacement, bd: Value 0 or 16 Bits or 32 Bits)6.4.3 Memory Indirect6.4.4 Memory Indirect with PC6.4.4.a PC Indirect with Index (8-Bit Displacement)6.4.4.b PC Indirect with Index (Base Displacement)6.4.4.c PC Indirect (Postindexed)6.4.4.d PC Indirect (Preindexed)6.5 68020 Instructions6.5.1 New Privileged Move Instruction6.5.2 Return and Delocate Instruction6.5.3 CHK/CHK2 and CMP/CMP2 Instructions6.5.4 Trap On Condition Instructions6.5.5 Bit Field Instructions6.5.6 Pack and Unpack Instructions6.5.7 Multiplication and Division Instructions6.5.8 MC68000 Enhanced Instructions
6.6 68020 Advanced Instructions
6.6.1 Breakpoint Instruction6.6.2 Call Module/Return from Module Instructions6.6.3 CAS Instuctions6.6.4 Coprocessor Instructions6.7 MC68020 Cache/Pipelined Architecture and Operation6.8 MC68020 Virtual Memory6.9 MC68020 Coprocessor Interface6.9.1 MC68881 Floating-Point Coprocessor6.9.1.a 68881 Data Movement Instructions6.9.1.b Monadic6.9.1.c Dyadic Instructions6.9.1.d BRANCH, Set, or Trap-On Condition6.9.1.e Miscellaneous Instructions6.9.2 MC68851 MMU6.10 MC68020 Pins and Signals6.11 MC68020 Timing Diagrams6.12 Exception Processing6.13 MC68020 System DesignQuestions and Problems
Chapter 7 Motorola MC68030/MC68040, Intel 80486 and Pentium Microprocessors
7.1 Motorola MC680307.1.1 MC68030 Block Diagram7.1.2 MC68030 Programming Model7.1.3 MC68030 Data Types, Addressing Modes, and Instructions7.1.3.a PMOVE Rn, (EA) or (EA), Rn7.1.3.b PTEST7.1.3.c PLOAD7.1.3.d PFLUSH7.1.4 MC68030 Cache7.1.5 68030 Pins and Signals7.1.6 MC68030 Read and Write Timing Diagrams7.1.7 MC68030 On-Chip Memory Management Unit7.1.7.a MMU Basics7.1.7.b 68030 On-chip MMU
7.2 MC68040
7.2.1 Introduction7.2.2 Register Architecture/Addressing Modes7.2.3 Instruction Set/Data Types7.2.4 68040 Processor Block Diagram7.2.5 68040 Memory Management7.2.6 Discussion and Conclusion7.3 Intel 80486 Microprocessor7.3.1 Intel 80486/80386 Comparison7.3.2 Special Features of the7.3.3 80486 New Instructions Beyond Those of the7.4 Intel Pentium Microprocessor7.4.1 Pentium Processor Block Diagram7.4.2 Pentium Registers7.4.3 Pentium Addressing Modes and Instructions7.4.4 Pentium Vs. 80486 Basic Differences in Registers, Paging, Stack Operations, and Exceptions7.4.4.a Registers of the Pentium Processor vs. Those of the7.4.4.b Paging7.4.4.c Stack Operations7.4.4.d Exceptions7.4.5 Input/Output7.4.6 Applications with the PentiumQuestions and Problems
Chapter 8 RISC Microprocessors: Intel 80960, Motorola MC88100 and PowerPC
8.1 Basics of RISC8.2 Intel8.2.1 Introduction8.2.2 Key Performance Features8.2.2.a Load and Store Model8.2.2.b Large Internal Register Sets8.2.2.c On-Chip Code and Data Checking8.2.2.d Overlapped Instruction Execution8.2.2.e Single Clock Instructions8.2.2.f Interrupt Model8.2.2.g Procedure Call Mechanism8.2.2.h Instruction Set and Addressing8.2.2.i Floating Point Unit (Available with 80960SB only)8.2.3 80960SA/SB Registers8.2.3.a Register Scoreboarding8.2.3.b Instruction Pointer8.2.3.c Process Control Register8.2.3.d Arithmetic Control8.2.4 Data Types and Addresses8.2.4.a Data Types8.2.4.b Literals8.2.4.c Register Addressing8.2.4.d Memory Addressing Modes8.2.5 809690SA/SB Instruction Set8.2.5.a Data Movement8.2.5.b Conversion (Available with 80960SB only)8.2.5.c Arithmetic and Logic Operations8.2.5.d Comparison and Control8.2.6 80960SA/SB Pins and Signals8.2.6.a Basic Bus States8.2.6.b Signals Groups8.2.7 Basic READ and WRITE8.2.8 80960SA/SB-Based Microcomputer8.3 Motorola MC88100 RISC Microprocessor8.3.1 88100/88200 Interface8.3.2 88100 Registers8.3.3 88100 Data Types, Addressing Modes, and Instructions8.3.4 88100 Pins and Signals8.3.5 88100 Exception Processing8.4 IBM/Motorola/Apple PowerPC8.4.1 PowerPC 601 Block Diagram8.4.1.a RTC (Real Time Clock)8.4.1.b Instruction Unit8.4.1.c Execution Unit8.4.1.d Memory Management Unit (MMU)8.4.1.e Cache Unit :8.4.1.f Memory Unit8.4.1.g System Interface8.4.2 Byte and Bit Ordering8.4.3 PowerPC Resigsters and Programming Model8.4.3.a User-Level Registers8.4.3.b Supervisor-Level Registers8.4.4 PowerPC 601 Memory Addressing: Effective Address (EA) Calculation8.4.4.a Register Indirect with Immediate Index Mode8.4.4.b Register Indirect with Index Mode8.4.5 PowerPC 601 Typical Instructions8.4.5.a Integer Instructions8.4.5.b Floating-Point Instructions8.4.5.c Load/Store Instructions8.4.5.d Flow Control Instructions8.4.5.e Processor Control Instructions8.4.6 PowerPC 601 Exception Model8.4.7 601 System Interface8.4.7.a Memory Accesses8.4.7.b I/O Controller Interface Operations8.4.7.c 601 Signals8.4.8 PowerPC 601 Vs. Alpha
8.5 64-Bit RISC Microprocessors
Questions and Problems
Chapter 9 Peripheral Interfacing
9.1 Keyboard Interface9.1.1 Basics of Keyboard and Display Interface to a Microprocessor9.1.2 8086 Keyboard Interface9.1.2.a Hardware9.1.2.b Software9.2 DMA Controllers9.3 Printer Interface9.3.1 LRC7040 Printer Interface Using Direct Microcomputer Control9.3.2 LRC7040 Printer Interface to a Microcomputer Using the 8295 Printer Controller Chip9.3.2.a 8295 Parallel Interface9.3.2.b 8295 Serial Mode9.4 CRT (Cathode Ray Tube) Controller and Graphics Controller Chips9.4.1 CRT Fundamentals9.4.2 Intel 8275 CRT Controller9.4.3 Intel 82786 Graphics Controller9.5 Coprocessors9.5.1 Intel 80879.5.2 Intel 802879.5.3 Intel 80387Questions and Problems
Chapter 10 Design Problems
10.1 Design Problem No. 110.1.1 Problem Statement10.1.2 Objective10.1.3 Operation10.1.4 Hardware10.1.5 Software10.2 Design Problem No. 210.2.1 Display Scroller Using the Intel 808610.2.1.a Introduction and Problem Statement10.2.1.b Hardware Description10.2.1.c Software Development10.3 Design Problem No. 310.3.1 Problem Statement10.3.2 Solution No. 110.3.2.a Hardware10.3.2.b Microcomputer Development System10.3.2.c Software10.3.3 Solution No. 210.3.3.a Hardware10.3.3.b SoftwareQuestions and Problems
Appendix A: The Hewlett-Packard (HP) 64000
Appendix B: Motorola MC68000 and Support Chips — Data Sheets
Appendix C: Intel 8085, 8086, and Support Chips — Data Sheets
Appendix D: MC68000 Instruction Execution Times
Appendix E: 8086 Instruction Set Reference Data
Appendix F: Glossary/ASCII Codes
Bibliography
Credits
Index

Content preview from Microprocessors and Microcomputer-Based System Design, 2nd Edition

APPENDIX D MC68000 INSTRUCTION EXECUTION TIMES

D.1 Introduction

This Appendix contains listings of the instruction execution times in terms of external clock (CLK) periods. In this data, it Is assumed that both memory read and write cycle times are four clock periods. A longer memory cycle will cause the generation of wait states which must be added to the total instruction time.

The number of bus read and write cycles for each Instruction is also included with the timing data. This data is enclosed in parenthesis following the number of clock periods and is shown as: (r/w) where r is the number of read cycles and w is the number of write cycles included in the clock period number. Recalling that either a read or write cycle requires four clock ...

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Microprocessors and Microcomputer-Based System Design, 2nd Edition

by Mohamed Rafiquzzaman

APPENDIX D MC68000 INSTRUCTION EXECUTION TIMES

D.1 Introduction

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