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Microprocessors and Microcontrollers by Pearson

Name: Microprocessors and Microcontrollers by Pearson
Author: Lyla B Das
ISBN: 9781299445468

by Lyla B Das

May 2024

Intermediate to advanced

616 pages

21h 36m

English

Pearson India

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Cover (1/2)
Cover (2/2)
Contents (1/2)
Contents (2/2)
Preface
About the Author
Roadmap to the Syllabus
Chapter 0: Basics of Computer Systems
0.1 A Brief History of Microprocessors
0.1.1 The x86 Family
0.1.2 The x86 Philosophy

0.1.3 Personal Computers
0.2 Basics of Computer Architecture
0.2.1 The Block Diagram of a Computer
0.2.2 The System Bus
0.2.3 The Processor
0.2.4 System Clock
0.2.5 Memory
0.2.6 The I/O System
0.3 Computer Languages
0.3.1 Machine Language, Assembly Language and High Level Language
0.3.2 Comparison
0.4 RISC and CISC Architectures
0.5 Number Systems
0.5.1 The Decimal System
0.5.2 The Binary Number System
0.5.3 The Hexadecimal Number System
0.6 Number Format Conversions
0.6.1 Conversion from Decimal to Binary
0.6.2 Conversion from Decimal to Hexadecimal
0.6.3 Converting from Binary to Hexadecimal
0.6.4 BCD Numbers
0.6.5 ASCII Code
0.6.6 Representation of Negative Numbers
0.7 Computer Arithmetic
0.7.1 Addition of Unsigned Numbers
0.7.2 Addition of Packed BCD Numbers
0.7.3 Addition of Negative Numbers
0.7.4 Subtraction
0.7.5 Packed BCD Subtraction
0.7.6 Subtraction of Signed Numbers
0.7.7 Addition of Numbers of Different Lengths
0.8 Units of Memory Capacity
0.9 The 8085 Microprocessor
0.9.1 The Programming Model of 8085
0.9.2 Assembly Language Programming
0.9.2.1 Modes of Addressing
0.9.3 Instruction set of 8085
0.9.3.1 Data Transfer Instructions0.9.3.2 Arithmetic Instructions0.9.3.3 Branch Instructions0.9.3.4 Logical and Bit Manipulation Instructions
0.9.4 Hardware Aspects of the 8085 (1/2)
0.9.4.1 Multiplexed Address/Data Bus0.9.4.2 Read and Write0.9.4.3 Power Supply and Clock0.9.4.4 Reset and Ready Pins0.9.4.5 Interrupt
0.9.4 Hardware Aspects of the 8085 (2/2)
0.9.4.6 Hold and HLDA0.9.4.7 SID and SOD
Key Points of this Chapter
Questions
Exercises
Chapter 1: The Architecture of 8086
1.1 Internal Block Diagram of the 80861.2 The Execution Unit
1.2.1 The Scratchpad Registers
1.2.2 Flag Register
1.3 Bus Interface Unit
1.3.1 The Instruction Queue1.3.2 Memory Segmentation1.3.2.1 Segment Registers1.3.2.2 The Code Segment and the Instruction Pointer1.3.2.3 The Stack Segment and the Stack Pointer1.3.2.4 The Data Segment and Extra Segment
1.4 Addressing Modes
Key Points of this Chapter
Questions
Exercises
Chapter 2: Programming Concepts – I
2.1 The Assembly Process
2.1.1 Features of Assemblers
2.1.2 Instructions and Directives2.1.3 The Forward Reference Problem
2.1.4 Two Pass Assemblers
2.2 Assemblers for x86
2.2.1 Why MASM?
2.2.2 Assembly Language Programming
2.3 Memory Models
2.3.1 The Tiny Model
2.3.2 COM and EXE Files
2.3.3 Definition of Data Types
2.3.4 The Small Model
2.3.5 The DUP Directive
2.3.6 The EQU Directive
2.3.7 The ORG Directive
2.3.8 Other Models
2.3.9 Full Segment Definition
2.3.10 General Rules for Writing Assembly Language
2.3.10 General Rules for Writing Assembly Language
2.4 Instruction Design
2.4.1 Manual Coding2.4.2 Instruction Set Architecture (ISA)
2.4.3 Instruction Set Design of 8086
2.4.4 Designing a Code
Key Points of this Chapter
Questions
Exercises
Chapter 3: Programming Concepts – II
3.1 Approaches to Programming
3.1.1 BIOS and DOS Function Calls
3.1.2 Using DOS Function Calls
3.1.3 The Instruction Set of 8086
3.2 Data Transfer Instructions3.2.1 MOV – Move
3.2.2 LEA – Load Effective Address
3.2.3 XLAT – Translate a Byte in AL
3.2.4 PUSH and POP
3.2.4.1 Operation of the Stack3.2.4.2 Defining a Stack
3.3 Branch Instructions
3.3.1 JMP – Jump3.3.1.1 The Near Jump3.3.1.2 The Short Jump
3.3.2 Other Forms of the Unconditional Jump Instruction
3.3.2.1 Conditional Jumps3.3.2.2 Far Jump
3.3.3 The LOOP Instruction
3.4 Arithmetic Instructions
3.4.1 Flag Control Instructions
3.4.2 Addition Instructions
3.4.3 Subtraction
3.4.4 Compare Instruction
3.4.5 Unsigned Multiplication
3.4.6 Unsigned Division
3.5 Logical Instructions
3.6 Shift and Rotate Instructions
3.6.1 Shift
3.6.2 Rotate Instructions
Key Points of this Chapter
Questions
Exercises
Chapter4: Programming Concepts – III
4.1 String Instructions
4.1.1 The MOVS Instruction
4.1.2 The CMPS Instruction
4.1.3 The SCAS Instruction
4.1.4 The STOS and LODS Instructions
4.2 Procedures
4.2.1 Writing a Procedure
4.2.2 Call and Return Instructions
4.2.2.1 Intrasegment or ‘Near’ Call
4.2.2.2 Intersegment or Far Call
4.2.3 The RET Instruction
4.2.4 The Use of the Stack in Procedure Calls
4.2.5 Passing Parameters To and From Procedures
4.2.5.1 Passing Parameters Through Registers4.2.5.2 Passing Parameters Through Memory4.2.5.3 Passing Parameters Through the Stack
4.3 Macros
4.3.1 Writing a Macro
4.3.2 Using the ‘Local’ Directive in Macros
4.4 Number Format Conversions
4.4.1 Packed BCD to Unpacked BCD Conversion
4.4.2 BCD Calculations
4.5 ASCII Operations
4.5.1 ASCII Addition
4.5.2 ASCII Subtraction
4.5.3 Multiplication and Division
4.6 Conversions for Computations and Display/Entry
4.6.1 Converting ASCII Numbers to Binary Form
4.6.2 Converting Binary Numbers to ASCII Form
4.7 Signed Number Arithmetic
4.7.1 Comparison of Signed Numbers
4.7.2 Signed Multiplication and Division
4.7.3 Arithmetic Shift
4.8 Programming Using High Level Language Constructs
Key Points of this Chapter
Questions
Exercises
Chapter 5: Programming Concepts – IV
5.1 Input/Output Programming
5.1.1 Memory Mapped I/O
5.1.2 Peripheral or Isolated I/O5.2 I/O Instructions
5.2.1 Fixed Port Addressing
5.2.2 Variable Port Addressing
5.3 Modular Programming
5.3.1 PUBLIC
5.3.2 EXTRN
5.3.3 Frequently Used Modules
5.4 Programming in C with Assembly Modules
Key Points of this Chapter
QuestionsExercises
Chapter 6: The Hardware Structure of 8086
6.1 Pin Configuration
6.1.1 Minimum Mode Pins
6.1.2 De-multiplexing the Address/Data Bus
6.1.3 Minimum Mode Pin Functions
6.1.4 The De-multiplexed Address/Data Bus
6.1.4.1The Address Bus
6.1.4.2 The Data Bus
6.1.5 Control Signals for Read and Write
6.1.6 Memory and I/O
6.1.7 Clock Generation6.1.8 Ready
6.1.9 Reset
6.1.10 Power on Reset
6.2 Clock
6.2.1 Read Machine Cycle
6.2.2 Wait Cycles
6.2.3 Write Machine Cycle
6.3 Other Processor Activities6.3.1 Interrupt Lines
6.3.2 DMA
6.3.3 TEST
6.3.4 Bus High Enable (BHE )6.3.5 Halt Machine Cycle
6.4 Maximum Mode
6.4.1 Bus Controller
6.4.2 Request/Grant pins
6.4.3 Queue Status pins QS0 , QS1
6.4.4 LOCK
6.5 Instruction Cycle
6.5.1 Delay Loops
6.5.2 Why Delay Loops?
Key Points of this Chapter
Questions
Exercises
Chapter 7: Memory and I/O Decoding
7.1 Memory Device Pins
7.2 Memory Address Decoding
7.2.1 Address Decoding Concepts
7.2.2 Address Decoding Using Block Decoders
7.2.3 Partial Address Decoding
7.3 Memory Banks
7.3.1 Odd Addresses Word
7.3.2 Why Memory Banks?
7.3.3 Using Separate Write Strobes
7.3.4 Memory Map of IBM-PC7.4 I/O Address Decoding
7.4.1 Output Ports
7.4.2 Input Ports
7.4.3 Decoding 16-Bit I/O Addresses
7.4.4 Ports with 16-Bit Data Bus
Key Points of this Chapter
QuestionsExercises
Chapter 8: The Interrupt Structure of 8086
8.1 Interrupts of 8086
8.1.1 Interrupt Response of 8086
8.1.2 Interrupt Service Routine and Interrupt Vector
8.1.3 Interrupt Vector Table
8.2 Dedicated Interrupt Types
8.2.1 INT 0 (Divide by Zero Error)
8.2.2 INT 1 (Single Stepping)
8.2.3 INT 2 (Non Maskable Interrupt)8.2.4 INT 3 (Breakpoint Interrupt)
8.2.5 INT 4 (Overfl ow Interrupt)
8.2.6 Allocation of Interrupt Type Numbers8.3 Software Interrupts
8.3.1 DOS and BIOS Interrupt Routines
8.4 Hardware Interrupts8.4.1 NMI8.4.2 INTR
8.5 Priority of Interrupts
8.6 Interrupt Type Allocation for Current PCs8.6.1 BIOS and DOS Interrupts8.6.2 BIOS 10H Functions
8.6.3 Video Adapter
8.6.4 History8.6.5 Text and Graphics
8.6.6 Character Display
8.6.7 Color Configuration
8.7 BIOS 10H Functions (1/2)
8.7 BIOS 10H Functions (2/2)
8.8 Addressing Video Memory Directly
8.9 Keyboard Interfacing
8.9.1 Computer Keyboard
8.9.2 Keyboard Hardware
8.9.2.1 Keyboard Controller8.9.2.2 Scan Code
8.9.3 Keyboard Interrupt Type 09
8.9.3.1 BIOS INT 09 Routine
8.9.4 BIOS 16H Functions
8.10 Hooking an Interrupt
8.10.1 Terminate and Stay Resident
8.10.2 DOS Functions for Interrupt Hooks
8.10.3 Hooking Into Hardware Interrupts (1/2)
8.10.3 Hooking Into Hardware Interrupts (2/2)
Key Points of this Chapter
Questions
Exercises
Chapter 9: Peripheral Interfacing – I
9.1 Trainer Kit
9.2 Programmable Peripheral Interface (PPI)-8255A
9.2.1 Pin Configuration and Internal Block Diagram
9.2.2 Programming the PPI
9.3 Modes of Operation
9.4 Mode 0
9.4.1 Interfacing 16 Bits I/O Ports to the 8255
9.4.2 Bit Set Reset Mode
9.5 Mode 1
9.5.1 Strobed Input Mode
9.5.2 Mode 1: Strobed Output (1/2)
9.5.2 Mode 1: Strobed Output (2/2)
9.6 Mode 2 (Strobed Bidirectional Bus I/O)
9.7 Centronics Printer Interface
9.7.1 History
9.8 Interfacing an Analog-to-Digital Converter to the 8086
9.9 Interfacing to a Digital-to-Analog Converter
9.10 Interfacing Liquid Crystal Displays to the 8086
9.10.1 Pins of the LCD
9.11 Interfacing a Stepper Motor to the 8086
9.11.1 Stepper Motor Types
9.11.2 Two-Phase Stepper Motors
9.11.3 Driving a Stepper Motor
9.11.3.1 Full Step Drive (two phases on)9.11.3.2 Wave drive9.11.3.3 Half stepping
9.11.4 Using the 8255 to Interface a Stepper Motor
9.11.5 Step Angle
9.11.6 Other Issues Regarding Stepper Motors
9.11.7 Optocouplers
9.12 Hex Keyboard Interfacing
9.12.1 Hex Keyboard9.12.2 Detecting a Keypress
9.12.3 Identifying the Key
9.12.4 Key Debounce
9.13 Interfacing LED Displays
9.13.1 Seven Segment LED
9.13.2 Static Seven Segment Displays
9.13.3 Dynamic Display
9.13.4 An Eight-Digit Dynamic, Multiplexed Display
Key Points of this Chapter
Questions
Exercises
Chapter 10: Peripheral Interfacing – II
10.1 The Programmable Interval Timer 8253/8254
10.1.1 Counters
10.1.2 Programming the Chip
10.1.3 Control Word
10.1.4 Using all the Counters
10.1.5 Mode 0: Interrupt on Terminal Count
10.1.6 Mode 1: Programmble One Shot
10.1.7 Mode 2: Rate Generator
10.1.8 Mode 3: Square Wave Generator
10.1.9 Mode 4: Software Triggered Mode10.1.10 Mode 5: Hardware Triggered Mode
10.1.11 Reading a Count
10.2 The Programmable Keyboard Display Interface – 827910.2.1 Display Interface
10.2.2 Segment Defi nition
10.2.3 Keyboard Section
10.2.4 System with Keyboard and Display Interfaced
10.2.5 Control Words
10.2.6 Detecting a Keypress
10.3 The Programmable Interrupt Controller (PIC) 8259
10.3.1 Introduction10.3.2 8259 – Features
10.3.3 Block Diagram
10.3.4 Interrupt Sequence for an 8086 Based System
10.3.5 Using the 8259
10.3.6 Initialization Command Words (ICWs)10.3.7 Initialization Sequence10.3.7.1 ICW1 (Initialization Command Word1)10.3.7.2 ICW2 (Initialization Command Word2)10.3.7.3 ICW3 (Initialization Control Word3)10.3.7.4 Initialization Command Word 4 (ICW4)
10.3.8 Operational Command Words
10.3.8.1 OCW 1 (Operational Command Word 1)10.3.8.2 OCW2 (Operational Control Word2)10.3.8.3 OCW3 (Operational Control Word 3)
10.4 Cascade Mode
10.4.1 Programmable Interrupt Controllers in the PC
Key Points of this Chapter
Questions
Exercises
Chapter 11: Peripheral Interfacing – III
11.1 Serial Communication Principles11.2 Simplex, Half Duplex and Full Duplex Communication
11.2.1 | Synchronous vs Asynchronous Communications
11.2.2 Asynchronous Communications
11.2.3 Transmission Rate
11.2.4 Modems
11.2.5 Baud Rate vs Bps
11.2.6 RS-232 Standards
11.2.7 RS-232 Level Converters
11.2.8 RS-232 Connectors11.2.9 DCE and DTE Devices
11.2.10 Handshaking in the RS232C Protocol
11.3 The Programmable Serial Communication Interface
11.3.1 Universal Asynchronous/Synchronous Receiver/Transmitter – USART 8251
11.3.2 Functional Block Diagram
11.3.2.1 Data Bus Buffer11.3.2.2 Transmitter Buffer11.3.2.3 Transmitter Control11.3.2.4 Receive Buffer11.3.2.5 Receiver Control11.3.2.6 R/W Control Block11.3.2.7 Modem Control Block
11.3.3 How This Chip Operates
11.3.4 Programming the 825111.3.5 Asynchronous Mode11.3.5.1 Mode Instruction Format11.3.5.2 Command Instruction Format
11.3. 6 Programming the 8251
11.4 Internal Reset on Power Up
11.5 Direct Memory Access
11.5.1 DMA Controller
11.5.2 Flyby DMA
11.5.3 Fetch and Deposit DMA
11.5.4 DMA Transfer Modes
11.5.5 DMA Controller Features
11.6 The DMA Controller – 8237
11.6.1 Programming the 8237 DMA Controller
11.6.2 Functional Block Diagram
11.6.3 Memory Addresses above 64 KB
11.6.4 Initialization and Programming the 8237
11.7 DMA and IBM-PC
11.7.1 DMA and PC-AT
11.8 PCI Based ComputersKey Points of this Chapter
Questions
Exercises
Chapter 12: The 8051 Microcontroller
12.1 Microprocessor vs Microcontroller12.1.1 Microprocessors
12.1.2 Microcontroller
12.1.3 Embedded Systems
12.1.4 Application Domain of Embedded Systems
12.2 History and Family Details of 8051
12.2.1 Other Members of the Family
12.2.2 Learning the Features of 8051
12.3 8051 – The Programmer’s Perspective12.3.1 Eight Bit Registers of 805112.3.1.1 The Accumulator Register ‘A’12.3.1.2 Register B12.3.1.3 Register Banks12.3.1.4 Processor Status Word (PSW)12.3.1.5 Stack Pointer (SP)
12.3.2 Internal Memory
12.3.2.1 Internal RAM12.3.2.2 Internal ROM12.3.3 Sixteen Bit Registers12.3.3.1 Program Counter (PC)12.3.3.2 Data Pointer (DPTR)
12.3.4 Ports
12.4 Assembly Language Programming12.4.1 Modes of Addressing12.4.1.1 Register Addressing12.4.1.2 Immediate Addressing12.4.1.3 Direct Addressing12.4.1.4 Register Indirect Addressing
12.4.1.5 Indexed Addressing
12.5 Internal RAM
12.6 The 8051 Stack
12.6.1 The Push Operation
12.6.2 The Pop Operation
12.7 Processor Status Word (PSW)
12.8 Assembler Directives
12.8.1 ORG12.8.2 EQU12.8.3 DB
12.8.4 BIT
12.8.5 END12.9 Storing Data in Code Memory (ROM)
12.10 The Instruction Set of 8051
12.10.1 Data Transfer Instructions
12.10.2 Bit Manipulation Instructions
12.10.3 Branch Instructions (1/4)
12.10.3.1 Unconditional Jump Instructions12.10.3.2 Conditional Branch Instructions12.10.3.3 Arithmetic Instructions
12.10.3 Branch Instructions (2/4)
12.10.3.4 Subtraction Instructions12.10.3.5 Multiplication Instruction12.10.3.6 Division Instruction12.10.3.7 Decimal Adjust for BCD Addition12.10.3.8 Clear the Accumulator12.10.3.9 Compare Instruction
12.10.3 Branch Instructions (3/4)
12.10.3.10 Port Programming12.10.3.11 Port Instructions12.10.3.12 Logical Instructions
12.10.3 Branch Instructions (4/4)
12.10.3.13 Complement12.10.3.14 Rotate Instructions
12.11 Subroutines (Procedures)
12.12 Delay Loops
12.12.1 Calculating Delay
12.12.2 Using NOP
Key Points of this Chapter
QuestionsExercises
Chapter 13: The 8051 Real Time Control
13.1 Pin Configuration of the 805113.1.1 The Crystal
13.1.2 Power on Reset
13.1.3 Port Pins
13.1.3.1 Output Stage of Port 0
13.1.4 Pins for External Memory Interfacing
13.2 Programming the Internal Peripherals13.3 Timers of the 8051
13.3.1 Interval Timer
13.3.2 Timer Programming
13.3.3 The Timer Mode Register (TMOD)
13.3.4 Clock Source for the Timer
13.3.5 Steps in Programming an Interval Timer
13.3.6 Writing the Mode Control Word
13.3.7 Mode 1 Programming13.3.7.1 Starting the Timer13.3.7.2 Detecting Timer Overflow13.3.7.3 Delay Calculation
13.3.8 Mode 2 Programming
13.4 Counter Programming
13.4.1 Measuring an Unknown Frequency
13.4.2 Event Counting
13.5 Interrupts of 8051
13.5.1 Enabling Interrupts
13.5.2 Using Timers in the Interrupt Mode
13.5.3 Steps in Using Timer 0 in the Interrupt-Driven Mode
13.5.4 External Hardware Interrupts
13.5.5 Edge Triggering of the External Interrupts
13.6 Serial Communication
13.6.1 Serial Transmission13.6.2 Serial Reception13.6.3 RS 232C
13.6.4 Baud Rates
13.6.5 Registers in the Uart of 8051
13.6.6 Modes13.6.7 The Transmit Interrupt (TI) Flag
13.6.8 Steps in Transmitting Data Serially
13.6.9 Serial Reception
13.6.9.1 Steps in Receiving Data Serially
13.7 Conclusion
Key Points of this ChapterQuestions
Exercises
Chapter 14: 80186 – The Embedded Microprocessor
14.1 History and Development of AVR
14.1.1 Risc Concepts Used in AVR
14.2 AVR Microcontroller Types
14.2.1 Understanding the AVR Architecture
14.2.2 The AVR Core14.2.2.1 On Chip Memory14.2.2.2 Program Counter14.2.2.3 Register File14.2.2.4 Data Address Pointers14.2.2.5 Status Register
14.2.2.6 The AVR Stack
14.3 The AVR ATMega16
14.3.1 Pin Diagram
14.3.2 General Purpose I/O
14.3.2.1 DDRx (Data Direction Register)14.3.2.2 PINx (Port in Register)14.3.2.3 PORTx (Port Register)
14.3.3 Memory Map of the Chip
14.3.4 Byte-addressable EEPROM
14.3. 5 Data Memory14.3.6 Timer Unit14.3.6.1 Clock Sources for the Timer Unit
14.3.7 Interrupts
14.3.8 Serial Communication
14.4 ConclusionKey Points of this Chapter
Questions
Exercises
Appendix A (1/3)
Appendix A (2/3)
Appendix A (3/3)
Appendix B (1/2)
Appendix B (2/2)
Appendix C (1/2)
Appendix C (2/2)
Appendix D (1/2)
Appendix D (2/2)
Appendix E (1/2)
Appendix E (2/2)
Appendix F
Bibliography
Model Question Papers (1/2)
Model Question Papers (2/2)
Index

Content preview from Microprocessors and Microcontrollers by Pearson

A.26 APPENDIX

Code Description 8086

HLT Halt 2

IDIV Integer division

8-bit reg 101–112

16-bit reg 165–184

8-bit mem (107–118)+EA

16-bit mem (171–190)+EA

IMUL Integer multiplication

8-bit reg 80–98

16-bit reg 128–154

8-bit mem (86–104)+EA

16-bit mem (134–160)+EA

IN Input from I /O port

Fixed port 10

Variable port through DX 8

INC Increment by 1

16-bit reg 3

8-bit reg 3

mem 15+EA

INT Interrupt

type=3 52

type3 51

INTO Interrupt if overﬂ ow

interrupt taken 53

interrupt not taken 4

IRET Return from interrupt 32

JA / Jump if above / 16, noj 4

JNBE Jump if not below or equal

JAE / Jump if above or equal 16, noj 4

JNB Jump if not below/

JNA Jump if not above

JCXZ Jump if CX is ...

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The X86 Microprocessors: Architecture and Programming (8086 to Pentium), 1st Edition

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by Lyla B Das

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