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Synchronization and Arbitration in Digital Systems by David J. Kinniment

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Contents

Preface

List of Contributors

Acknowledgements

1 Synchronization, Arbitration and Choice

1.1 Introduction

1.2 The Problem of Choice

1.3 Choice in Electronics

1.4 Arbitration

1.5 Continuous and Discrete Quantities

1.6 Timing

1.7 Book Structure

Part I

2 Modelling Metastability

2.1 The Synchronizer

2.2 Latch Model

2.3 Failure Rates

2.3.1 Event Histograms and MTBF

2.4 Latches and Flip-flops

2.5 Clock Back Edge

3 Circuits

3.1 Latches and Metastability Filters

3.2 Effects of Filtering

3.3 The Jamb Latch

3.3.1 Jamb Latch Flip-flop

3.4 Low Coupling Latch

3.5 The Q-flop

3.6 The MUTEX

3.7 Robust Synchronizer

3.8 The Tri-flop

4 Noise and its Effects

4.1 Noise

4.2 Effect of Noise on a Synchronizer

4.3 Malicious Inputs

4.3.1 Synchronous Systems

4.3.2 Asynchronous Systems

5 Metastability Measurements

5.1 Circuit Simulation

5.1.1 Time Step Control

5.1.2 Long-term τ

5.1.3 Using Bisection

5.2 Synchronizer Flip-flop Testing

5.3 Rising and Falling Edges

5.4 Delay-based Measurement

5.5 Deep Metastability

5.6 Back Edge Measurement

5.7 Measure and Select

5.7.1 Failure Measurement

5.7.2 Synchronizer Selection

6 Conclusions Part I

Part II

7 Synchronizers in Systems

7.1 Latency and Throughput

7.2 FIFO Synchronizer

7.3 Avoiding Synchronization

7.4 Predictive Synchronizers

7.5 Other Low-latency Synchronizers

7.5.1 Locally Delayed Latching (LDL)

7.5.2 Speculative Synchronization

7.6 Asynchronous Communication Mechanisms (ACM)

7.6.1 Slot Mechanisms

7.6.2 Three-slot Mechanism

7.6.3 Four-slot Mechanism ...

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