Synchronization and Arbitration in Digital Systems

5

Metastability Measurements

5.1 CIRCUIT SIMULATION

Metastability is an analog phenomenon, and so the performance of a circuit can be simulated by a circuit simulator such as SPICE. Predicting synchronizer failure rates, however, is difficult because the aim of a synchronizer is to give a very low failure rate, so that the probability of failure after the synchronization time has elapsed is around 10⁻¹⁵. This means that the voltage difference between the two flip-flop nodes when it enters metastability is very small, at around V_dd × 10⁻¹⁵. Circuit simulators are software based, and run on digital processors, so represent the voltages and currents in the circuit by means of floating point numbers, which are limited in their range and accuracy. Expressing two voltages of around 1 V to an accuracy of better than 10⁻¹⁵ V requires more than the usual word length used in conventional simulators and each increase in synchronization time requires a corresponding increase in the number of bits needed to represent the variables. Other problems are that below 1 mV node difference noise becomes important, the synchronizer response is nondeterministic, and so the results of a deterministic simulation may, or may not be a true representation of the results in practice. Typically the noise voltage dominates below about V_dd × 10⁻⁴ so below this point it must be assumed that statistically noise has no effect on MTBF. Simulation can be carried out in the deterministic region, and can provide a useful ...