June 2001
Intermediate to advanced
759 pages
20h 17m
English
Content preview from The Designer's Guide to VHDL, 2nd Edition
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21 Miscellaneous Topics
In the preceding chapters we have introduced most of the facilities provided by VHDL and shown how they may be used to model a variety of hardware systems at various levels of detail. However, there remain a few VHDL facilities that we have not yet discussed. In this chapter, we tie off these loose ends.
21.1 Buffer and Linkage Ports
When we introduced ports in Chapter 5, we identified three modes, in, out and inout, that control how data is passed to and from a design entity. VHDL provides two further modes, buffer and linkage. These modes may only be specified for ports of entities, blocks and components, not for generic constants or subprogram parameters.
A buffer mode port behaves in a similar way to an inout
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