References
- Cortex-M0 Devices Generic User Guide (DUI 0497A)
The User Guide (UG) provides the list of Cortex-M0 features with a brief explanation on each. UG includes the complete instruction set, which would be useful in chapters 4–11 while writing programs in assembly language. UG also explains the exception model and details of the system peripherals SysTick and NVIC, which would help you go deeper into exception and interrupt handling, covered in chapters 10, 11 and 18. For most parts of this book, UG should provide a reasonably good first-level reference.
- Cortex-M0 Technical Reference Manual (Revision: r0p0)
The Technical Reference Manual (TRM) is a brief (∼70 pages!) yet comprehensive document that provides a summary of all the blocks of Cortex-M0. After providing a summary, TRM points to the respective section in the Armv6-M Architecture Reference Manual for more details.
- Armv6-M Architecture Reference Manual (DDI 041C)
Armv6-M Architecture Reference Manual (Armv6-M ARM), is the ‘mother’ document for all the processors based on Armv6-M architecture, including Cortex-M0. It contains complete details about the architecture: registers, instruction set, memory model, exception model and details of system peripherals SysTick and NVIC.
Armv6-M ARM contains two sections: Application-Level Architecture and System-Level Architecture. The “Application-Level Architecture” section describes registers, instruction set and memory model. There is a section on “Alphabetical list of ...
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