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Analog Integrated Circuit Design, 2nd Edition

Name: Analog Integrated Circuit Design, 2nd Edition
ISBN: 9780470770108

by Tony Chan Carusone, David A. Johns, Kenneth W. Martin

December 2011

Intermediate to advanced

816 pages

27h 8m

English

Wiley

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Coverpage
Titlepage
Copyright
Dedication
Preface
Contents
Chapter 1 Integrated-Circuit Devices and Modelling
1.1 Semiconductors and pn Junctions1.1.1 Diodes1.1.2 Reverse-Biased Diodes1.1.3 Graded Junctions1.1.4 Large-Signal Junction Capacitance1.1.5 Forward-Biased Junctions1.1.6 Junction Capacitance of Forward-Biased Diode1.1.7 Small-Signal Model of a Forward-Biased Diode1.1.8 Schottky Diodes1.2 MOS Transistors1.2.1 Symbols for MOS Transistors1.2.2 Basic Operation1.2.3 Large-Signal Modelling1.2.4 Body Effect1.2.5 p-Channel Transistors1.2.6 Low-Frequency Small-Signal Modelling in the Active Region1.2.7 High-Frequency Small-Signal Modelling in the Active Region1.2.8 Small-Signal Modelling in the Triode and Cutoff Regions1.2.9 Analog Figures of Merit and Trade-offs1.3 Device Model Summary1.3.1 Constants1.3.2 Diode Equations1.3.3 MOS Transistor Equations1.4 Advanced MOS Modelling1.4.1 Subthreshold Operation1.4.2 Mobility Degradation1.4.3 Summary of Subthreshold and Mobility Degradation Equations1.4.4 Parasitic Resistances1.4.5 Short-Channel Effects1.4.6 Leakage Currents1.5 SPICE Modelling Parameters1.5.1 Diode Model1.5.2 MOS Transistors1.5.3 Advanced SPICE Models of MOS Transistors1.6 Passive Devices1.6.1 Resistors1.6.2 Capacitors1.7 Appendix1.7.1 Diode Exponential Relationship1.7.2 Diode-Diffusion Capacitance1.7.3 MOS Threshold Voltage and the Body Effect1.7.4 MOS Triode Relationship1.8 Key Points1.9 References1.10 Problems
Chapter 2 Processing and Layout
2.1 CMOS Processing2.1.1 The Silicon Wafer2.1.2 Photolithography and Well Definition2.1.3 Diffusion and Ion Implantation2.1.4 Chemical Vapor Deposition and Defining the Active Regions2.1.5 Transistor Isolation2.1.6 Gate-Oxide and Threshold-Voltage Adjustments2.1.7 Polysilicon Gate Formation2.1.8 Implanting the Junctions, Depositing SiO2, and Opening Contact Holes2.1.9 Annealing, Depositing and Patterning Metal, and Overglass Deposition2.1.10 Additional Processing Steps2.2 CMOS Layout and Design Rules2.2.1 Spacing Rulesy2.2.2 Planarity and Fill Requirements2.2.3 Antenna Rules2.2.4 Latch-Up2.3 Variability and Mismatch2.3.1 Systematic Variations Including Proximity Effects2.3.2 Process Variations2.3.3 Random Variations and Mismatch2.4 Analog Layout Considerations2.4.1 Transistor Layouts2.4.2 Capacitor Matching2.4.3 Resistor Layout2.4.4 Noise Considerations2.5 Key Points2.6 References2.7 Problems
Chapter 3 Basic Current Mirrors and Single-Stage Amplifiers
3.1 Simple CMOS Current Mirror3.2 Common-Source Amplifier3.3 Source-Follower or Common-Drain Amplifier3.4 Common-Gate Amplifier3.5 Source-Degenerated Current Mirrors3.6 Cascode Current Mirrors3.7 Cascode Gain Stage3.8 MOS Differential Pair and Gain Stage3.9 Key Points3.10 References3.11 Problems
Chapter 4 Frequency Response of Electronic Circuits
4.1 Frequency Response of Linear Systems4.1.1 Magnitude and Phase Response4.1.2 First-Order Circuits4.1.3 Second-Order Low-Pass Transfer Functions with Real Poles4.1.4 Bode Plots4.1.5 Second-Order Low-Pass Transfer Functions with Complex Poles4.2 Frequency Response of Elementary Transistor Circuits4.2.1 High-Frequency MOS Small-Signal Model4.2.2 Common-Source Amplifier4.2.3 Miller Theorem and Miller Effect4.2.4 Zero-Value Time-Constant Analysis4.2.5 Common-Source Design Examples4.2.6 Common-Gate Amplifier4.3 Cascode Gain Stage4.4 Source-Follower Amplifier4.5 Differential Pair4.5.1 High-Frequency T-Model4.5.2 Symmetric Differential Amplifier4.5.3 Single-Ended Differential Amplifier4.5.4 Differential Pair with Active Load4.6 Key Points4.7 References4.8 Problems

Chapter 5 Feedback Amplifiers
5.1 Ideal Model of Negative Feedback5.1.1 Basic Definitions5.1.2 Gain Sensitivity5.1.3 Bandwidth5.1.4 Linearity5.1.5 Summary5.2 Dynamic Response of Feedback Amplifiers5.2.1 Stability Criteria5.2.2 Phase Margin5.3 First- and Second-Order Feedback Systems5.3.1 First-Order Feedback Systems5.3.2 Second-Order Feedback Systems5.3.3 Higher-Order Feedback Systems5.4 Common Feedback Amplifiers5.4.1 Obtaining the Loop Gain, L(s)5.4.2 Non-Inverting Amplifier5.4.3 Transimpedance (Inverting) Amplifiers5.5 Summary of Key Points5.6 References5.7 Problems
Chapter 6 Basic Opamp Design and Compensation
6.1 Two-Stage CMOS Opamp6.1.1 Opamp Gain6.1.2 Frequency Response6.1.3 Slew Rate6.1.4 n-Channel or p-Channel Input Stage6.1.5 Systematic Offset Voltage6.2 Opamp Compensation6.2.1 Dominant-Pole Compensation and Lead Compensation6.2.2 Compensating the Two-Stage Opamp6.2.3 Making Compensation Independent of Process and Temperature6.3 Advanced Current Mirrors6.3.1 Wide-Swing Current Mirrors6.3.2 Enhanced Output-Impedance Current Mirrors and Gain Boosting6.3.3 Wide-Swing Current Mirror with Enhanced Output Impedance6.3.4 Current-Mirror Symbol6.4 Folded-Cascode Opamp6.4.1 Small-Signal Analysis6.4.2 Slew Rate6.5 Current Mirror Opamp6.6 Linear Settling Time Revisited6.7 Fully Differential Opamps6.7.1 Fully Differential Folded-Cascode Opamp6.7.2 Alternative Fully Differential Opamps6.7.3 Low Supply Voltage Opamps6.8 Common-Mode Feedback Circuits6.9 Summary of Key Points6.10 References6.11 Problems
Chapter 7 Biasing, References, and Regulators
7.1 Analog Integrated Circuit Biasing7.1.1 Bias Circuits7.1.2 Reference Circuits7.1.3 Regulator Circuits7.2 Establishing Constant Transconductance7.2.1 Basic Constant-Transconductance Circuit7.2.2 Improved Constant-Transconductance Circuits7.3 Establishing Constant Voltages and Currents7.3.1 Bandgap Voltage Reference Basics7.3.2 Circuits for Bandgap References7.3.3 Low-Voltage Bandgap Reference7.3.4 Current Reference7.4 Voltage Regulation7.4.1 Regulator Specifications7.4.2 Feedback Analysis7.4.3 Low Dropout Regulators7.5 Summary of Key Points7.6 References7.7 Problems
Chapter 8 Bipolar Devices and Circuits
8.1 Bipolar-Junction Transistors8.1.1 Basic Operation8.1.2 Analog Figures of Merit8.2 Bipolar Device Model Summary8.3 SPICE Modeling8.4 Bipolar and BICMOS Processing8.4.1 Bipolar Processing8.4.2 Modern SiGe BiCMOS HBT Processing8.4.3 Mismatch in Bipolar Devices8.5 Bipolar Current Mirrors and Gain Stages8.5.1 Current Mirrors8.5.2 Emitter Follower8.5.3 Bipolar Differential Pair8.6 Appendix8.6.1 Bipolar Transistor Exponential Relationship8.6.2 Base Charge Storage of an Active BJT8.7 Summary of Key Points8.8 References8.9 Problems
Chapter 9 Noise and Linearity Analysis and Modelling
9.1 Time-Domain Analysis9.1.1 Root Mean Square (rms) Value9.1.2 SNR9.1.3 Units of dBm9.1.4 Noise Summation9.2 Frequency-Domain Analysis9.2.1 Noise Spectral Density9.2.2 White Noise9.2.3 1/f, or Flicker, Noise9.2.4 Filtered Noise9.2.5 Noise Bandwidth9.2.6 Piecewise Integration of Noise9.2.7 1/f Noise Tangent Principle9.3 Noise Models for Circuit Elements9.3.1 Resistors9.3.2 Diodes9.3.3 Bipolar Transistors9.3.4 MOSFETS9.3.5 Opamps9.3.6 Capacitors and Inductors9.3.7 Sampled Signal Noise9.3.8 Input-Referred Noise9.4 Noise Analysis Examples9.4.1 Opamp Example9.4.2 Bipolar Common-Emitter Example9.4.3 CMOS Differential Pair Example9.4.4 Fiber-Optic Transimpedance Amplifier Example9.5 Dynamic Range Performance9.5.1 Total Harmonic Distortion (THD)9.5.2 Third-Order Intercept Point (IP3)9.5.3 Spurious-Free Dynamic Range (SFDR)9.5.4 Signal-to-Noise and Distortion Ratio (SNDR)9.6 Key Points9.7 References9.8 Problems
Chapter 10 Comparators
10.1 Comparator Specifications10.1.1 Input Offset and Noise10.1.2 Hysteresis10.2 Using an Opamp for a Comparator10.2.1 Input-Offset Voltage Errors10.3 Charge-Injection Errors10.3.1 Making Charge-Injection Signal Independent10.3.2 Minimizing Errors Due to Charge-Injection10.3.3 Speed of Multi-Stage Comparators10.4 Latched Comparators10.4.1 Latch-Mode Time Constant10.4.2 Latch Offset10.5 Examples of CMOS and BiCMOS Comparators10.5.1 Input-Transistor Charge Trapping10.6 Examples of Bipolar Comparators10.7 Key Points10.8 References10.9 Problems
Chapter 11 Sample-and-Hold and Translinear Circuits
11.1 Performance of Sample-and-Hold Circuits11.1.1 Testing Sample and Holds11.2 MOS Sample-and-Hold Basics11.3 Examples of CMOS S/H Circuits11.4 Bipolar and BiCMOS Sample-and-Holds11.5 Translinear Gain Cell11.6 Translinear Multiplier11.7 Key Points11.8 References11.9 Problems
Chapter 12 Continuous-Time Filters
12.1 Introduction to Continuous-Time Filters12.1.1 First-Order Filters12.1.2 Second-Order Filters12.2 Introduction to Gm-C Filters12.2.1 Integrators and Summers12.2.2 Fully Differential Integrators12.2.3 First-Order Filter12.2.4 Biquad Filter12.3 Transconductors Using Fixed Resistors12.4 CMOS Transconductors Using Triode Transistors12.4.1 Transconductors Using a Fixed-Bias Triode Transistor12.4.2 Transconductors Using Varying Bias-Triode Transistors12.4.3 Transconductors Using Constant Drain-Source Voltages12.5 CMOS Transconductors Using Active Transistors12.5.1 CMOS Pair12.5.2 Constant Sum of Gate-Source Voltages12.5.3 Source-Connected Differential Pair12.5.4 Inverter-Based12.5.5 Differential-Pair with Floating Voltage Sources12.5.6 Bias-Offset Cross-Coupled Differential Pairs12.6 Bipolar Transconductors12.6.1 Gain-Cell Transconductors12.6.2 Transconductors Using Multiple Differential Pairs12.7 BiCMOS Transconductors12.7.1 Tunable MOS in Triode12.7.2 Fixed-Resistor Transconductor with a Translinear Multiplier12.7.3 Fixed Active MOS Transconductor with a Translinear Multiplier12.8 Active RC and MOSFET-C Filters12.8.1 Active RC Filters12.8.2 MOSFET-C Two-Transistor Integrators12.8.3 Four-Transistor Integrators12.8.4 R-MOSFET-C Filters12.9 Tuning Circuitry12.9.1 Tuning Overview12.9.2 Constant Transconductance12.9.3 Frequency Tuning12.9.4 Q-Factor Tuning12.9.5 Tuning Methods Based on Adaptive Filtering12.10 Introduction to Complex Filters12.10.1 Complex Signal Processing12.10.2 Complex Operations12.10.3 Complex Filters12.10.4 Frequency-Translated Analog Filters12.11 Key Points12.12 References12.13 Problems
Chapter 13 Discrete-Time Signals
13.1 Overview of Some Signal Spectra13.2 Laplace Transforms of Discrete-Time Signals13.2.1 Spectra of Discrete-Time Signals13.3 z-Transform13.4 Downsampling and Upsampling13.5 Discrete-Time Filters13.5.1 Frequency Response of Discrete-Time Filters13.5.2 Stability of Discrete-Time Filters13.5.3 IIR and FIR Filters13.5.4 Bilinear Transform13.6 Sample-and-Hold Response13.7 Key Points13.8 References13.9 Problems
Chapter 14 Switched-Capacitor Circuits
14.1 Basic Building Blocks14.1.1 Opamps14.1.2 Capacitors14.1.3 Switches14.1.4 Nonoverlapping Clocks14.2 Basic Operation and Analysis14.2.1 Resistor Equivalence of a Switched Capacitor14.2.2 Parasitic-Sensitive Integrator14.2.3 Parasitic-Insensitive Integrators14.2.4 Signal-Flow-Graph Analysis14.3 Noise in Switched-Capacitor Circuits14.4 First-Order Filters14.4.1 Switch Sharing14.4.2 Fully Differential Filters14.5 Biquad Filters14.5.1 Low-Q Biquad Filter14.5.2 High-Q Biquad Filter14.6 Charge Injection14.7 Switched-Capacitor Gain Circuits14.7.1 Parallel Resistor-Capacitor Circuit14.7.2 Resettable Gain Circuit14.7.3 Capacitive-Reset Gain Circuit14.8 Correlated Double-Sampling Techniques14.9 Other Switched-Capacitor Circuits14.9.1 Amplitude Modulator14.9.2 Full-Wave Rectifier14.9.3 Peak Detectors14.9.4 Voltage-Controlled Oscillator14.9.5 Sinusoidal Oscillator14.10 Key Points14.11 References14.12 Problems
Chapter 15 Data Converter Fundamentals
15.1 Ideal D/A Converter15.2 Ideal A/D Converter15.3 Quantization Noise15.3.1 Deterministic Approach15.3.2 Stochastic Approach15.4 Signed Codes15.5 Performance Limitations15.5.1 Resolution15.5.2 Offset and Gain Error15.5.3 Accuracy and Linearity15.6 Key Points15.7 References15.8 Problems
Chapter 16 Nyquist-Rate D/A Converters
16.1 Decoder-Based Converters16.1.1 Resistor String Converters16.1.2 Folded Resistor-String Converters16.1.3 Multiple Resistor-String Converters16.1.4 Signed Outputs16.2 Binary-Scaled Converters16.2.1 Binary-Weighted Resistor Converters16.2.2 Reduced-Resistance-Ratio Ladders16.2.3 R-2R-Based Converters16.2.4 Charge-Redistribution Switched-Capacitor Converters16.2.5 Current-Mode Converters16.2.6 Glitches16.3 Thermometer-Code Converters16.3.1 Thermometer-Code Current-Mode D/A Converters16.3.2 Single-Supply Positive-Output Converters16.3.3 Dynamically Matched Current Sources16.4 Hybrid Converters16.4.1 Resistor-Capacitor Hybrid Converters16.4.2 Segmented Converters16.5 Key Points16.6 References16.7 Problems
Chapter 17 Nyquist-Rate A/D Converters
17.1 Integrating Converters17.2 Successive-Approximation Converters17.2.1 DAC-Based Successive Approximation17.2.2 Charge-Redistribution A/D17.2.3 Resistor-Capacitor Hybrid17.2.4 Speed Estimate for Charge-Redistribution Converters17.2.5 Error Correction in Successive-Approximation Converters17.2.6 Multi-Bit Successive-Approximation17.3 Algorithmic (or Cyclic) A/D Converter17.3.1 Ratio-Independent Algorithmic Converter17.4 Pipelined A/D Converters17.4.1 One-Bit-Per-Stage Pipelined Converter17.4.2 1.5 Bit Per Stage Pipelined Converter17.4.3 Pipelined Converter Circuits17.4.4 Generalized k-Bit-Per-Stage Pipelined Converters17.5 Flash Converters17.5.1 Issues in Designing Flash A/D Converters17.6 Two-Step A/D Converters17.6.1 Two-Step Converter with Digital Error Correction17.7 Interpolating A/D Converters17.8 Folding A/D Converters17.9 Time-Interleaved A/D Converters17.10 Key Points17.11 References17.12 Problems
Chapter 18 Oversampling Converters
18.1 Oversampling without Noise Shaping18.1.1 Quantization Noise Modelling18.1.2 White Noise Assumption18.1.3 Oversampling Advantage18.1.4 The Advantage of 1-Bit D/A Converters18.2 Oversampling with Noise Shaping18.2.1 Noise-Shaped Delta-Sigma Modulator18.2.2 First-Order Noise Shaping18.2.3 Switched-Capacitor Realization of a First-Order A/D Converter18.2.4 Second-Order Noise Shaping18.2.5 Noise Transfer-Function Curves18.2.6 Quantization Noise Power of 1-Bit Modulators18.2.7 Error-Feedback Structure18.3 System Architectures18.3.1 System Architecture of Delta-Sigma A/D Converters18.3.2 System Architecture of Delta-Sigma D/A Converters18.4 Digital Decimation Filters18.4.1 Multi-Stage18.4.2 Single Stage18.5 Higher-Order Modulators18.5.1 Interpolative Architecture18.5.2 Multi-Stage Noise Shaping (MASH) Architecture18.6 Bandpass Oversampling Converters18.7 Practical Considerations18.7.1 Stability18.7.2 Linearity of Two-Level Converters18.7.3 Idle Tones18.7.4 Dithering18.7.5 Opamp Gain18.8 Multi-Bit Oversampling Converters18.8.1 Dynamic Element Matching18.8.2 Dynamically Matched Current Source D/S Converters18.8.3 Digital Calibration A/D Converter18.8.4 A/D with Both Multi-Bit and Single-Bit Feedback18.9 Third-Order A/D Design Example18.10 Key Points18.11 References18.12 Problems
Chapter 19 Phase-Locked Loops
19.1 Basic Phase-Locked Loop Architecture19.1.1 Voltage Controlled Oscillator19.1.2 Divider19.1.3 Phase Detector19.1.4 Loop Filer19.1.5 The PLL in Lock19.2 Linearized Small-Signal Analysis19.2.1 Second-Order PLL Model19.2.2 Limitations of the Second-Order Small-Signal Model19.2.3 PLL Design Example19.3 Jitter and Phase Noise19.3.1 Period Jitter19.3.2 P-Cycle Jitter19.3.3 Adjacent Period Jitter19.3.4 Other Spectral Representations of Jitter19.3.5 Probability Density Function of Jitter19.4 Electronic Oscillators19.4.1 Ring Oscillators19.4.2 LC Oscillators19.4.3 Phase Noise of Oscillators19.5 Jitter and Phase Noise in PLLS19.5.1 Input Phase Noise and Divider Phase Noise19.5.2 VCO Phase Noise19.5.3 Loop Filter Noise19.6 Key Points19.7 References19.8 Problems
Index

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Analog Integrated Circuit Design, 2nd Edition

by Tony Chan Carusone, David A. Johns, Kenneth W. Martin

Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
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