Distributed and Parallel Computing

15Power Optimization in 4Bit Comparator Architecture Through Precomputation Technique

Adarsh Sharma¹, Suman Lata Tripathi^2*, Deepika Ghai¹ and Khilda Afifah³

¹School of Electrical and Electronics Engineering, Lovely Professional University, Jalandhar Punjab, India

²Department of Electronics and Communication Engineering, Symbiosis Institute of Technology (SIT), Symbiosis International (Deemed University), Pune, India

³School of Electrical Engineering & Management, Telkom University, Bandung, West Java, Indonesia

Abstract

Efficient power consumption is a critical requirement in modern digital systems, especially for resource-constrained applications. This paper presents an optimized 4-bit comparator design employing the precomputation technique to significantly reduce power dissipation. By precomputing partial results and minimizing unnecessary transitions, the proposed design achieves enhanced power efficiency without compromising performance or accuracy. The methodology involves partitioning the comparison process into smaller, power-efficient stages, reducing dynamic power consumption by mitigating redundant switching activities. Simulation results validate the effectiveness of the approach, demonstrating substantial power savings compared to conventional designs while maintaining competitive delay characteristics. This study underscores the potential of precomputation in advancing low-power digital circuit designs. The circuits were implemented using Cadence Virtuoso Tool ...