Avoid Branching

Modern processors tend not to be particularly branch friendly. In the “good old days” one processor instruction would finish before the next instruction was issued. This meant that if one instruction calculated the target for a branch or set a condition code on which a branch decision was dependent, the result of this instruction was available for immediate use by the next instruction. This made for a simple processor architecture, though generally not a particularly fast one.

Almost all modern processors are now pipelined. A pipelined processor breaks up instruction execution into a number of stages. A simple pipeline might have five stages: instruction fetch, instruction decode, operand fetch, operation execution, and result ...

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