Practical Electronic Design for Experimenters

APPENDIX DHow to Use Karnaugh Maps

Supplement to Chapter 11 and Related Solutions

Karnaugh maps, or K-maps, are a graphical technique for minimizing digital logic circuits. They are no longer widely used, but they are technically interesting. Most digital circuits are implemented with microcontrollers or programmable logic these days, so there is little need to simplify a complex logic circuit. Simulation and logic synthesis software has also taken away the need for a minimization step. However, if you are still designing with basic TTL or CMOS logic gates, flip flops, and functional ICs, using K-maps can lead to some savings. If you are curious about K-maps, this appendix will give you an introduction and a few design examples. Only “real” ...