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RISC-V Architecture and DSP Processor Design

Name: RISC-V Architecture and DSP Processor Design
Author: Zhang Zhiwei
ISBN: 9781807600891

by Zhang Zhiwei

April 2026

Intermediate

280 pages

7h 54m

English

Packt Publishing

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Preface
Chapter 1: Introduction to Digital Signal Processors
Prerequisite knowledgeThe development history of digital signal processorsFirst-generation DSPsSecond-generation DSPsThird-generation DSPsFourth-generation DSPsDSP evolution after 2010CEVA's DSP core IP product lineCadence's DSP core IP product lineMain features of digital signal processorsInstruction setHarvard architectureDeterministic memory designPing-pong memory architectureData formats and algorithmsArithmetic unitHardware implementation of arithmetic operationsDesign trade-offs in arithmetic unit implementationEvolution of arithmetic unitsAddressing modesApplication fields of digital signal processorsIndustrial controlNew energyElectric vehiclesSummary
Chapter 2: The RISC-V Architecture
The development history of RISC-VAdvantages of RISC-VTechnical advantagesEcosystem advantagesOpen source and licensing advantages of RISC-VMain features of RISC-VModular designBasic integer instruction setM extensionF extensionC extensionZifencei extensionZicsr extensionPrivileged architectureRISC-V open-source projectsUniversity of California, BerkeleyPULP organizationOpenHW organizationlowRISC organizationPingtougeBeijing Open Source Chip Research InstituteIndian Institute of Technology MadrasSummary
Chapter 3: SpringCore Architecture
Design goals of SpringCoreProcessor featuresMemory featuresDigital signal processing algorithmsInstruction set designSupported data typesStructural registersControl and status registersEncoding summaryInstruction extensionArchitecture designCore architectureInstruction fetch unitDecoder unitControl unitExecution unitMemory access unitStorage spaceSummary
Chapter 4: SpringCore Pipeline Design
Introduction to pipeline technologyPipeline segmentationInstruction fetch unitInstruction fetch unit structureInstruction alignmentDecode unitPre-decodingBasic decodingException detectionInstruction dispatchData dependencyStructural hazardsControl dependenciesPipeline low power controlLoop controlControl and status registersSummary
Chapter 5: Memory Access Architecture
SpringCore storage architectureStorage attributes and protectionPhysical memory attributesSecurity domainMemory access protection mechanismMemory access module designMemory access pipelineMemory consistencySignificance of memory consistencyMemory consistency modelsSequential synchronization instructions and atomic instructionsSummary
Chapter 6: Arithmetic Units
Fixed-point arithmetic unit designStructure of fixed-point arithmetic unitCarry-lookahead adderSaturation processingBooth-Wallace tree multiplierGeneral descriptionImplementation detailsThe Wallace tree compression methodGeneral descriptionImplementation detailsMultiply-accumulate unitShifterRadix-4 SRT dividerGeneral descriptionImplementation detailsFloating-point arithmetic unit designFloating-point data formatFloating-point control and status registerStructure of the floating-point execution unitFloating-point multiply-accumulate unitChoice of path number in three-path algorithmsFloating-point division and square root unitImplementation process of floating-point division and square root operationsSummary
Chapter 7: Exception and Interrupt Mechanisms
Understanding exceptions and interruptsInterrupt handling mechanismInterrupt types in RISC-V architectureSoftware interruptsTimer interruptsExternal interruptsNon-maskable interruptsProcessor interrupt controllerInterrupt controller specifications in RISC-VWhy SpringCore uses the CLICCLIC memory-mapped control registersCLIC-related CSRsInterrupt arbitration processInterrupt handling processInterrupt nestingTail-chaining interruptLate-arriving interruptSummary
Chapter 8: Debugging Unit Design
Introduction to JTAGJTAG backgroundJTAG interfaceTAP controllerStructure of the debug unitOverview of the debug unitDebug transport moduleDebug moduleDebug module control and status informationAbstract commandsData registers for parameters and return valuesRead-only program memory regionsProgram bufferSignificance of abstract commandOn-chip debug supportDebug handling mechanismDebugging processReset control and run controlAbstract commandDebug function implementation examplesSingle-step debuggingAccessing continuous memory regionsSummary
Chapter 9: Software Development Environment
Technical requirementsCompilerLLVM workflowLLVM backend processing flowDirected acyclic graphText representation of the DAGInstruction legalizationCall loweringAssemblers and DisassemblersWorking ProcessUsageLinkerChoice of linkerLinker relaxationStack growth directionEmulatorSimulator software architectureSimulator custom developmentDebuggerOverview of debugger solutionsIntroduction to GDBIntroduction to OpenOCDIntegrated development environmentSoftware framework and plugin developmentProject creation and managementToolchain integration and configurationDebugging schemeSummary

Chapter 10: SpringCore-based DSP Chips
Exploring the FDM320RV335Key technical featuresUnderstanding the functional architectureAccessing peripheral registersWorking with DMAReviewing pin descriptionMapping the address spacePeripheral frame registersConfiguring low power modesGetting started with the prototype boardMeasuring chip performanceSummary
Index

Content preview from RISC-V Architecture and DSP Processor Design

7 Exception and Interrupt Mechanisms

The processor's exception and interrupt mechanism refers to the processor's ability to promptly respond to certain abnormal execution situations in a program or external events during the normal execution flow, and correctly return to the original program execution position after the handling is complete. Exception and interrupt mechanisms are key processing mechanisms for processors, ensuring the stability and reliability of computer system operation, as well as the real-time response to external events. This chapter will use SpringCore as an example to introduce the processor's exception and interrupt mechanisms.

In this chapter, we will cover the following topics:

Understanding exceptions and interrupts ...

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RISC-V Architecture and DSP Processor Design

by Zhang Zhiwei

7

Exception and Interrupt Mechanisms

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