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The Definitive Guide to the ARM Cortex-M3

Name: The Definitive Guide to the ARM Cortex-M3
Author: Joseph Yiu
ISBN: 9780080551432

by Joseph Yiu

April 2011

Intermediate to advanced

384 pages

8h 13m

English

Newnes

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Cover
Title Page
Copyright
Foreword
Preface
Acknowledgments
Terms and Abbreviations
Conventions
References
Table of Contents

Chapter 1: Introduction
What Is the ARM Cortex-M3 Processor?Background of ARM and ARM ArchitectureInstruction Set DevelopmentThe Thumb-2 Instruction Set Architecture (ISA)Cortex-M3 Processor ApplicationsOrganization of This BookFurther Readings
Chapter 2: Overview of the Cortex-M3
FundamentalsRegistersOperation ModesThe Built-In Nested Vectored Interrupt ControllerThe Memory MapThe Bus InterfaceThe Memory Protection UnitThe Instruction SetInterrupts and ExceptionsDebugging SupportCharacteristics Summary
Chapter 3: Cortex-M3 Basics
RegistersSpecial RegistersOperation ModeExceptions and InterruptsVector TablesStack Memory OperationsReset Sequence
Chapter 4: Instruction Sets
Assembly BasicsInstruction ListInstruction DescriptionsSeveral Useful Instructions in the Cortex-M3
Chapter 5: Memory Systems
Memory System Features OverviewMemory MapsMemory Access AttributesDefault Memory Access PermissionsBit-Band OperationsUnaligned TransfersExclusive AccessesEndian Mode
Chapter 6: Cortex-M3 Implementation Overview
The PipelineA Detailed Block DiagramBus Interfaces on the Cortex-M3Other Interfaces on the Cortex-M3The External Private Peripheral BusTypical ConnectionsReset Signals
Chapter 7: Exceptions
Exception TypesDefinitions of PriorityVector TablesInterrupt Inputs and Pending BehaviorFault ExceptionsSVC and PendSV
Chapter 8: The NVIC and Interrupt Control
NVIC OverviewThe Basic Interrupt ConfigurationInterrupt Enable and Clear EnableInterrupt Pending and Clear PendingExample Procedures in Setting Up an InterruptSoftware InterruptsThe SYSTICK Timer
Chapter 9: Interrupt Behavior
Interrupt/Exception SequencesException ExitsNested InterruptsTail-Chaining InterruptsLate ArrivalsMore on the Exception Return ValueInterrupt LatencyFaults Related to Interrupts
Chapter 10: Cortex-M3 Programming
OverviewThe Interface Between Assembly and CA Typical Development FlowThe First StepProducing OutputsUsing Data MemoryUsing Exclusive Access for SemaphoresUsing Bit-Band for SemaphoresWorking with Bit Field Extract and Table Branch
Chapter 11: Exceptions Programming
Using InterruptsException/Interrupt HandlersSoftware InterruptsExample with Exception HandlersUsing SVCSVC Example: Use for Output FunctionsUsing SVC with C
Chapter 12: Advanced Programming Features and System Behavior
Running a System with Two Separate StacksDouble-Word Stack AlignmentNonbase Thread EnablePerformance ConsiderationsLockup Situations
Chapter 13: The Memory Protection Unit
OverviewMPU RegistersSetting Up the MPUTypical Setup
Chapter 14: Other Cortex-M3 Features
The SYSTICK TimerPower ManagementMultiprocessor CommunicationSelf-Reset Control
Chapter 15: Debug Architecture
Debugging Features OverviewCoreSight OverviewDebug ModesDebugging EventsBreakpoint in the Cortex-M3Accessing Register Content in DebugOther Core Debugging Features
Chapter 16: Debugging Components
IntroductionTrace Components: Data Watchpoint and TraceTrace Components: Instrumentation Trace MacrocellTrace Components: Embedded Trace MacrocellTrace Components: Trace Port Interface UnitThe Flash Patch and Breakpoint UnitThe AHB Access PortROM Table
Chapter 17: Getting Started with Cortex-M3 Development
Choosing a Cortex-M3 ProductDifferences Between Cortex-M3 Revision 0 and Revision 1Development Tools
Chapter 18: Porting Applications from the ARM7 to the Cortex-M3
OverviewSystem CharacteristicsAssembly Language FilesC Program FilesPrecompiled Object FilesOptimization
Chapter 19: Starting Cortex-M3 Development Using the GNU Tool Chain
BackgroundGetting the GNU Tool ChainDevelopment FlowExamplesAccessing Special RegistersUsing Unsupported InstructionsInline Assembler in the GNU C Compiler
Chapter 20: Getting Started with the KEIL RealView Microcontroller Development Kit
OverviewGetting Started with μVisionOutputting the “Hello World” Message Via UARTTesting the SoftwareUsing the DebuggerThe Instruction Set SimulatorModifying the Vector TableStopwatch Example with Interrupts
APPENDIX A: Cortex-M3 Instructions Summary
Supported 16-Bit Thumb InstructionsSupported 32-Bit Thumb-2 Instructions
APPENDIX B: 16-Bit Thumb Instructions and Architecture Versions
APPENDIX C: Cortex-M3 Exceptions Quick Reference
Exception Types and EnablesStack Contents After Exception Stacking
APPENDIX D: NVIC Registers Quick Reference
APPENDIX E: Cortex-M3 Troubleshooting Guide
OverviewDeveloping Fault HandlersOther Possible Problems
Index
Instructions for online access

Content preview from The Definitive Guide to the ARM Cortex-M3

CHAPTER 6 Cortex-M3 Implementation Overview

In This Chapter:

• The Pipeline

• A Detailed Block Diagram

• Bus Interfaces on the Cortex-M3

• Other Interfaces on the Cortex-M3

• The External Private Peripheral Bus

• Typical Connections

• Reset Signals

The Pipeline

The Cortex-M3 processor has a three-stage pipeline. The pipeline stages are instruction fetch, instruction decode, and instruction execution (see Figure 6.1).

Figure 6.1 The Three-Stage Pipeline in the Cortex-M3

Some people might argue that there are four stages because of the pipeline behavior in the bus interface when it accesses memory, but this stage is outside the processor, ...

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The Definitive Guide to the ARM Cortex-M3

by Joseph Yiu

The Pipeline

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