CHAPTER 6 Cortex-M3 Implementation Overview
In This Chapter:
The Cortex-M3 processor has a three-stage pipeline. The pipeline stages are instruction fetch, instruction decode, and instruction execution (see Figure 6.1).
Figure 6.1 The Three-Stage Pipeline in the Cortex-M3
Some people might argue that there are four stages because of the pipeline behavior in the bus interface when it accesses memory, but this stage is outside the processor, ...