Design for Embedded Image Processing on FPGAs, 2nd Edition

2Field‐programmable Gate Arrays

In this chapter, the basic architectural features of field‐programmable gate arrays (FPGAs) are examined. While a detailed understanding of the internal architecture of an FPGA is not essential to programme them (the vendor‐specific place‐and‐route tools manage most of these details), a basic knowledge of the internal structure and how a design maps onto that architecture can be used to develop a more efficient implementation.

The approaches commonly used to programme FPGAs are then outlined. The concept of register transfer level (RTL) design is introduced, and the key characteristics of hardware description languages (HDLs) described. This culminates in a discussion of high‐level synthesis (HLS) for algorithm implementation.

Finally, the opportunities for realising image processing algorithms on FPGAs are outlined, with advice on choosing an appropriate development board for image processing.

2.1 Hardware Architecture of FPGAs

The basic idea behind programmable hardware is to have a generic circuit where the functionality can be programmed for a particular application. Computers are based on this idea, where the arithmetic logic unit (ALU) can perform one of several operations based on a set of control signals. The limitation of an ALU is that it can only perform one operation at a time. Therefore, a particular application must be decomposed into the sequence of control signals for controlling the function of the ALU, along with the logic ...