Design for Embedded Image Processing on FPGAs, 2nd Edition

6Interfacing

An image processing system never stands alone. This is particularly the case for an embedded vision system, which is usually designed for one specific purpose or task. Therefore, there are usually one or more peripheral devices connected to the field‐programmable gate array (FPGA) implementing the system.

Each device must have an appropriate interface within the FPGA. This is responsible for passing any data to, or from, the application logic, including any format conversions required between the peripheral and the algorithm. It is also responsible for providing any control signals required by the peripheral. This may range from a clock signal and simple handshaking through to complex protocol management. Many peripheral devices require initialisation or configuration through the setting of control registers.

The interface logic may be considered to be a device driver, shielding the image processing hardware from the lower level complexities of the physical interface (Bailey et al., 2006). In this context, the term device driver refers primarily to the interface hardware and control signals. This chapter focuses on some of the techniques associated with the design of such interfaces.

It is also useful within this context to consider the interaction between the FPGA system and the user. On a hosted system, many of the user‐interface tasks will be performed using the host operating system. However, on a stand‐alone system, all of these functions must be performed ...