Design for Embedded Image Processing on FPGAs, 2nd Edition

Preface

Image processing, and in particular embedded image processing, faces many challenges, from increasing resolution, increasing frame rates, and the need to operate at low power. These offer significant challenges for implementation on conventional software‐based platforms. This leads naturally to considering field‐programmable gate arrays (FPGAs) as an implementation platform for embedded imaging applications. Many image processing operations are inherently parallel, and FPGAs provide programmable hardware, also inherently parallel. Therefore, it should be as simple as mapping one onto the other, right? Well, yes …and no.

Image processing is traditionally thought of as a software domain task, whereas FPGA‐based design is firmly in the hardware domain. There are a lot of tricks and techniques required to create an efficient design. Perhaps the biggest hurdle to an efficient implementation is the need for a hardware mindset. To bridge the gap between software and hardware, it is necessary to think of algorithms not on their own but more in terms of their underlying computational architecture. Implementing an image processing algorithm (or indeed any algorithm) on an FPGA therefore consists of determining the underlying architecture of an algorithm, mapping that architecture onto the resources available within an FPGA, and finally mapping the algorithm onto the hardware architecture. While the mechanics of this process is mostly automated by high‐level synthesis tools, the ...