book

Dynamic RAM

Name: Dynamic RAM
Author: Muzaffer A. Siddiqi
ISBN: 9781351832588

by Muzaffer A. Siddiqi

December 2017

Intermediate to advanced

382 pages

12h 19m

English

CRC Press

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Cover
Half Title
Title Page
Copyright Page
Table of Contents
Preface
Acknowledgments
1 Random Access Memories
1.1 Inroduction1.2 Static Random Access Memory1.3 Dynamic Random Access Memories: Basics1.3.1 Three-Transistor DRAM Cell1.3.1.1 Construction and Operation1.4 One-Transistor DRAM Cell1.4.1 One-Transistor DRAM Structures and Switching Waveforms—Review1.5 Initial-Stage DRAM Technology Developments1.5.1 Sense Amplifiers1.5.2 Open and Folded Bit-Line Structures1.6 DRAM Operating Modes1.6.1 Asynchronous Modes1.6.2 Control Logic1.6.3 Synchronous Modes1.6.4 Double Data Rate SDRAM1.7 Silicon-on-Insulator Technology1.7.1 Capacitor-Less DRAMs1.8 Advanced Nonvolatile Memories1.8.1 Flash Memories1.8.2 Ferroelectric RAM (FRAM)1.8.3 Magnetoresistive RAM (MRAM)1.8.3.1 Spin-Torque-Transfer (STT) MRAM1.8.4 Phase Change RAM (PRAM)References
2 DRAM Cell Development
2.1 Introduction2.2 Planar DRAM Cell2.3 Three-Dimensional Capacitor DRAM Cell2.3.1 First-Generation Trench Capacitor Cell2.3.1.1 Corrugated Capacitor Cell2.3.1.2 Folded Capacitor Cell2.3.1.3 Vertical Capacitor Cell2.3.1.4 Isolation-Merged Vertical Capacitor and Buried Isolation Capacitor Cells2.3.1.5 FASIC Cell2.3.2 Second-Generation Inverted-Type Trench Cells2.3.2.1 Substrate Plate Trench-Capacitor Cell2.3.2.2 Dielectrically Encapsulated Trench Cell2.3.2.3 Half-Vcc Sheath-Plate Capacitor Cell2.3.2.4 Double Stacked Capacitor with Self-Aligned Poly Drain/Source Transistor Cell2.4 Access Transistor Stacked above Trench Capacitor Cell2.4.1 Trench Transistor with Self-Aligned Contact Cell2.5 Trench Transistor Cell2.6 Buried Storage Electrode Cell2.7 Buried Capacitor or Stacked Transistor Cell2.8 Stacked Capacitor Cells2.8.1 Horizontal and Vertical Fin Structured Capacitor CellsReferences
3 DRAM Technologies
3.1 Introduction3.2 DRAM Technology—Early Stage Development3.2.1 Mixed NMOS/CMOS DRAM3.3 Two-Dimensional DRAM Cell3.4 16 Mbit–256 Mbit, 1 Gbit DRAM Development3.4.1 Crown-Shaped Stacked Capacitor Cell Technology3.4.2 Tantalum Pentoxide (Ta2O5)-Based Storage Capacitor3.5 Capacitor over Bit Line (COB) DRAM CellReferences

4 Advanced DRAM Cell Transistors
4.1 Introduction4.2 Recess-Channel-Array Transistor4.2.1 Sphere-Shaped RCAT4.3 Vertical Depleted Lean-Channel Transistor Structure4.3.1 Double Gate MOSFET4.4 FinFET—A Self-Aligned DG-MOSFET4.5 Body Tied MOSFETs/Bulk FinFETs4.6 Multichannel FET4.7 Saddle MOSFET4.8 Saddle FinFET4.9 Surrounding Gate Transistor4.9.1 Multipillar SGT4.10 Three-Dimensional Memory Architecture: Cell Area Less than 4 F24.10.1 Stacked-Surrounding Gate Transistor and Cell4.11 BEST and VERIBEST DRAM Cells4.12 Vertical Transistors4.13 Advanced Recessed FinFETsReferences
5 Storage Capacitor Enhancement Techniques
5.1 Introduction5.2 Hemispherical Grain Storage Node5.3 Higher Permittivity and Layered Dielectrics5.3.1 Ta2O5-Based Capacitors5.4 Low-Temperature HSG5.5 Sub-100 nm Trench Capacitor DRAMs5.6 Metal Insulator Metal Structure5.6.1 Ru/Ta2O5/Ru Capacitor Technology5.6.2 (BaxSrx) TiO3 (BST)-Based Storage Capacitor5.6.3 HfO2-Based Capacitor Technology5.6.4 ZrO2-Based DRAM Capacitor5.6.5 Advanced MIM CapacitorsReferences
6 Advanced DRAM Technologies
6.1 Introduction6.2 Advanced Cell Structures6.3 Robust Memory Cell—Mechanical Stability of Storage Node6.4 DRAM Cell Transistor Technology6.5 Cell Capacitor Technology6.6 Lithography Technology6.6.1 Extreme UV Lithography6.7 Isolation Techniques6.8 Bit Line, Word Line, and Gate Technology6.9 Cell Connections6.10 Interconnection/Metallization Technology6.10.1 Carbon Nanotubes and Graphene Nanoribbon-Based Interconnects6.11 Advanced DRAM Technology Developments6.11.1 0.18 μm to 0.11 μm DRAM Technology Development6.11.2 100 nm to 50 nm DRAM Technology Development6.11.3 Sub-50 nm DRAM Technology Development6.11.4 Sub-100 nm Trench DRAM Technology Development6.12 Embedded DRAMsReferences
7 Leakages in DRAMs
7.1 Introduction7.2 Leakage Currents in DRAMs7.2.1 Junction Leakage and Sub-Threshold Currents7.3 Power Dissipation in DRAMs7.4 Cell Signal Charge7.5 Power Dissipation for Data Retention7.6 Low-Power Schemes in DRAM7.6.1 Bit Line Capacitance and Its Reduction7.6.1.1 Refresh Time7.6.2 CMOS Technology7.6.3 On-Chip Voltage Reduction/Conversion7.6.4 Signal-to-Noise Ratio7.7 On-Chip Voltage Converter Circuits7.7.1 Back-Bias Generator7.7.2 Voltage Limiting Schemes7.8 Refresh Time Extension7.9 Sub-Threshold Current Reduction7.10 Multithreshold Voltage CMOS Schemes7.10.1 Stacking Effect and Leakage Reduction7.10.2 Sleepy Stack Concept7.10.3 Importance of Transistor Sizing7.11 VGS Reverse Biasing7.11.1 Offset Gate Driving7.11.2 Substrate Driving7.11.3 Offset Source Driving7.11.4 Simultaneous Negative Word Line and Reverse Body Bias Control7.12 Leakage Current Reduction Techniques in DRAMs7.13 Analysis of Sub-Threshold Leakage Reduction7.14 Sub-Threshold Leakage Reduction for Low-Voltage Applications7.15 Data Retention Time and Its ImprovementReferences
8 Memory Peripheral Circuits
8.1 Introduction8.2 Address Decoder Basics8.2.1 Row Decoders8.2.1.1 Dynamic Decoders8.2.2 Column Decoders8.3 Address Decoding Developments8.3.1 Multiplexed Address Buffer and Predecoding8.3.2 Static Column Operation8.4 DRAM Sense Amplifiers8.4.1 Gated Flip-Flop Sense Amplifier8.4.2 Charge-Transfer Sense Amplifier8.4.3 Threshold-Voltage Mismatch Compensated Sense Amplifiers8.4.4 Low-Voltage Charge-Transferred Presensing8.5 Error Checking and Correction8.6 On-Chip Redundancy Techniques and ECC8.7 Redundancy Schemes for High-Density DRAMs8.7.1 Subarray Replacement Redundancy for ISB Faults8.7.2 Flexible Redundancy Technique8.7.3 Inter-Subarray Replacement Redundancy8.7.4 DRAM Architecture-Based Redundancy TechniquesReferences
Index

Overview

Dynamic RAM (DRAM) has wide applications in the computer industry, telecommunications, the military, and the space industry. This book presents an up-to-date account of the theory and design of DRAM, the workhorse of all semiconductor memories. It summarizes the development of and recent advances in manufacturing technology, generation by generation. The text also addresses DRAM cell development capacitor enhancement technologies, different types of leakages, and the circuit and technological aspects of the remedial measures taken.

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