Dynamic RAM

Book description

Because of their widespread use in mainframes, PCs, and mobile audio and video devices, DRAMs are being manufactured in ever increasing volume, both in stand-alone and in embedded form as part of a system on chip. Due to the optimum design of their components—access transistor, storage capacitor, and peripherals—DRAMs are the cheapest and densest semiconductor memory currently available. As a result, most of DRAM structure research and development focuses on the technology used for its constituent components and their interconnections. However, only a few books are available on semiconductor memories in general and fewer on DRAMs.

Dynamic RAM: Technology Advancements provides a holistic view of the DRAM technology with a systematic description of the advancements in the field since the 1970s, and an analysis of future challenges.

Topics Include:

  • DRAM cells of all types, including planar, three-dimensional (3-D) trench or stacked, COB or CUB, vertical, and mechanically robust cells using advanced transistors and storage capacitors
  • Advancements in transistor technology for the RCAT, SCAT, FinFET, BT FinFET, Saddle and advanced recess type, and storage capacitor realizations
  • How sub 100 nm trench DRAM technologies and sub 50 nm stacked DRAM technologies and related topics may lead to new research
  • Various types of leakages and power consumption reduction methods in active and sleep mode
  • Various types of SAs and yield enhancement techniques employing ECC and redundancy

A worthwhile addition to semiconductor memory research, academicians and researchers interested in the design and optimization of high-density and cost-efficient DRAMs may also find it useful as part of a graduate-level course.

Table of contents

  1. Cover
  2. Half Title
  3. Title Page
  4. Copyright Page
  5. Table of Contents
  6. Preface
  7. Acknowledgments
  8. 1 Random Access Memories
    1. 1.1 Inroduction
    2. 1.2 Static Random Access Memory
    3. 1.3 Dynamic Random Access Memories: Basics
      1. 1.3.1 Three-Transistor DRAM Cell
        1. 1.3.1.1 Construction and Operation
    4. 1.4 One-Transistor DRAM Cell
      1. 1.4.1 One-Transistor DRAM Structures and Switching Waveforms—Review
    5. 1.5 Initial-Stage DRAM Technology Developments
      1. 1.5.1 Sense Amplifiers
      2. 1.5.2 Open and Folded Bit-Line Structures
    6. 1.6 DRAM Operating Modes
      1. 1.6.1 Asynchronous Modes
      2. 1.6.2 Control Logic
      3. 1.6.3 Synchronous Modes
      4. 1.6.4 Double Data Rate SDRAM
    7. 1.7 Silicon-on-Insulator Technology
      1. 1.7.1 Capacitor-Less DRAMs
    8. 1.8 Advanced Nonvolatile Memories
      1. 1.8.1 Flash Memories
      2. 1.8.2 Ferroelectric RAM (FRAM)
      3. 1.8.3 Magnetoresistive RAM (MRAM)
        1. 1.8.3.1 Spin-Torque-Transfer (STT) MRAM
      4. 1.8.4 Phase Change RAM (PRAM)
    9. References
  9. 2 DRAM Cell Development
    1. 2.1 Introduction
    2. 2.2 Planar DRAM Cell
    3. 2.3 Three-Dimensional Capacitor DRAM Cell
      1. 2.3.1 First-Generation Trench Capacitor Cell
        1. 2.3.1.1 Corrugated Capacitor Cell
        2. 2.3.1.2 Folded Capacitor Cell
        3. 2.3.1.3 Vertical Capacitor Cell
        4. 2.3.1.4 Isolation-Merged Vertical Capacitor and Buried Isolation Capacitor Cells
        5. 2.3.1.5 FASIC Cell
      2. 2.3.2 Second-Generation Inverted-Type Trench Cells
        1. 2.3.2.1 Substrate Plate Trench-Capacitor Cell
        2. 2.3.2.2 Dielectrically Encapsulated Trench Cell
        3. 2.3.2.3 Half-Vcc Sheath-Plate Capacitor Cell
        4. 2.3.2.4 Double Stacked Capacitor with Self-Aligned Poly Drain/Source Transistor Cell
    4. 2.4 Access Transistor Stacked above Trench Capacitor Cell
      1. 2.4.1 Trench Transistor with Self-Aligned Contact Cell
    5. 2.5 Trench Transistor Cell
    6. 2.6 Buried Storage Electrode Cell
    7. 2.7 Buried Capacitor or Stacked Transistor Cell
    8. 2.8 Stacked Capacitor Cells
      1. 2.8.1 Horizontal and Vertical Fin Structured Capacitor Cells
    9. References
  10. 3 DRAM Technologies
    1. 3.1 Introduction
    2. 3.2 DRAM Technology—Early Stage Development
      1. 3.2.1 Mixed NMOS/CMOS DRAM
    3. 3.3 Two-Dimensional DRAM Cell
    4. 3.4 16 Mbit–256 Mbit, 1 Gbit DRAM Development
      1. 3.4.1 Crown-Shaped Stacked Capacitor Cell Technology
      2. 3.4.2 Tantalum Pentoxide (Ta2O5)-Based Storage Capacitor
    5. 3.5 Capacitor over Bit Line (COB) DRAM Cell
    6. References
  11. 4 Advanced DRAM Cell Transistors
    1. 4.1 Introduction
    2. 4.2 Recess-Channel-Array Transistor
      1. 4.2.1 Sphere-Shaped RCAT
    3. 4.3 Vertical Depleted Lean-Channel Transistor Structure
      1. 4.3.1 Double Gate MOSFET
    4. 4.4 FinFET—A Self-Aligned DG-MOSFET
    5. 4.5 Body Tied MOSFETs/Bulk FinFETs
    6. 4.6 Multichannel FET
    7. 4.7 Saddle MOSFET
    8. 4.8 Saddle FinFET
    9. 4.9 Surrounding Gate Transistor
      1. 4.9.1 Multipillar SGT
    10. 4.10 Three-Dimensional Memory Architecture: Cell Area Less than 4 F2
      1. 4.10.1 Stacked-Surrounding Gate Transistor and Cell
    11. 4.11 BEST and VERIBEST DRAM Cells
    12. 4.12 Vertical Transistors
    13. 4.13 Advanced Recessed FinFETs
    14. References
  12. 5 Storage Capacitor Enhancement Techniques
    1. 5.1 Introduction
    2. 5.2 Hemispherical Grain Storage Node
    3. 5.3 Higher Permittivity and Layered Dielectrics
      1. 5.3.1 Ta2O5-Based Capacitors
    4. 5.4 Low-Temperature HSG
    5. 5.5 Sub-100 nm Trench Capacitor DRAMs
    6. 5.6 Metal Insulator Metal Structure
      1. 5.6.1 Ru/Ta2O5/Ru Capacitor Technology
      2. 5.6.2 (BaxSrx) TiO3 (BST)-Based Storage Capacitor
      3. 5.6.3 HfO2-Based Capacitor Technology
      4. 5.6.4 ZrO2-Based DRAM Capacitor
      5. 5.6.5 Advanced MIM Capacitors
    7. References
  13. 6 Advanced DRAM Technologies
    1. 6.1 Introduction
    2. 6.2 Advanced Cell Structures
    3. 6.3 Robust Memory Cell—Mechanical Stability of Storage Node
    4. 6.4 DRAM Cell Transistor Technology
    5. 6.5 Cell Capacitor Technology
    6. 6.6 Lithography Technology
      1. 6.6.1 Extreme UV Lithography
    7. 6.7 Isolation Techniques
    8. 6.8 Bit Line, Word Line, and Gate Technology
    9. 6.9 Cell Connections
    10. 6.10 Interconnection/Metallization Technology
      1. 6.10.1 Carbon Nanotubes and Graphene Nanoribbon-Based Interconnects
    11. 6.11 Advanced DRAM Technology Developments
      1. 6.11.1 0.18 μm to 0.11 μm DRAM Technology Development
      2. 6.11.2 100 nm to 50 nm DRAM Technology Development
      3. 6.11.3 Sub-50 nm DRAM Technology Development
      4. 6.11.4 Sub-100 nm Trench DRAM Technology Development
    12. 6.12 Embedded DRAMs
    13. References
  14. 7 Leakages in DRAMs
    1. 7.1 Introduction
    2. 7.2 Leakage Currents in DRAMs
      1. 7.2.1 Junction Leakage and Sub-Threshold Currents
    3. 7.3 Power Dissipation in DRAMs
    4. 7.4 Cell Signal Charge
    5. 7.5 Power Dissipation for Data Retention
    6. 7.6 Low-Power Schemes in DRAM
      1. 7.6.1 Bit Line Capacitance and Its Reduction
        1. 7.6.1.1 Refresh Time
      2. 7.6.2 CMOS Technology
      3. 7.6.3 On-Chip Voltage Reduction/Conversion
      4. 7.6.4 Signal-to-Noise Ratio
    7. 7.7 On-Chip Voltage Converter Circuits
      1. 7.7.1 Back-Bias Generator
      2. 7.7.2 Voltage Limiting Schemes
    8. 7.8 Refresh Time Extension
    9. 7.9 Sub-Threshold Current Reduction
    10. 7.10 Multithreshold Voltage CMOS Schemes
      1. 7.10.1 Stacking Effect and Leakage Reduction
      2. 7.10.2 Sleepy Stack Concept
      3. 7.10.3 Importance of Transistor Sizing
    11. 7.11 VGS Reverse Biasing
      1. 7.11.1 Offset Gate Driving
      2. 7.11.2 Substrate Driving
      3. 7.11.3 Offset Source Driving
      4. 7.11.4 Simultaneous Negative Word Line and Reverse Body Bias Control
    12. 7.12 Leakage Current Reduction Techniques in DRAMs
    13. 7.13 Analysis of Sub-Threshold Leakage Reduction
    14. 7.14 Sub-Threshold Leakage Reduction for Low-Voltage Applications
    15. 7.15 Data Retention Time and Its Improvement
    16. References
  15. 8 Memory Peripheral Circuits
    1. 8.1 Introduction
    2. 8.2 Address Decoder Basics
      1. 8.2.1 Row Decoders
        1. 8.2.1.1 Dynamic Decoders
      2. 8.2.2 Column Decoders
    3. 8.3 Address Decoding Developments
      1. 8.3.1 Multiplexed Address Buffer and Predecoding
      2. 8.3.2 Static Column Operation
    4. 8.4 DRAM Sense Amplifiers
      1. 8.4.1 Gated Flip-Flop Sense Amplifier
      2. 8.4.2 Charge-Transfer Sense Amplifier
      3. 8.4.3 Threshold-Voltage Mismatch Compensated Sense Amplifiers
      4. 8.4.4 Low-Voltage Charge-Transferred Presensing
    5. 8.5 Error Checking and Correction
    6. 8.6 On-Chip Redundancy Techniques and ECC
    7. 8.7 Redundancy Schemes for High-Density DRAMs
      1. 8.7.1 Subarray Replacement Redundancy for ISB Faults
      2. 8.7.2 Flexible Redundancy Technique
      3. 8.7.3 Inter-Subarray Replacement Redundancy
      4. 8.7.4 DRAM Architecture-Based Redundancy Techniques
    8. References
  16. Index

Product information

  • Title: Dynamic RAM
  • Author(s): Muzaffer A. Siddiqi
  • Release date: December 2017
  • Publisher(s): CRC Press
  • ISBN: 9781351832588