FSM-based Digital Design using Verilog HDL

FSM-based Digital Design using Verilog HDL

by Peter Minns, Ian Elliott
Released May 2008
Publisher(s): Wiley
ISBN: 9780470060704

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Book description

As digital circuit elements decrease in physical size, resulting in increasingly complex systems, a basic logic model that can be used in the control and design of a range of semiconductor devices is vital. Finite State Machines (FSM) have numerous advantages; they can be applied to many areas (including motor control, and signal and serial data identification to name a few) and they use less logic than their alternatives, leading to the development of faster digital hardware systems.

This clear and logical book presents a range of novel techniques for the rapid and reliable design of digital systems using FSMs, detailing exactly how and where they can be implemented. With a practical approach, it covers synchronous and asynchronous FSMs in the design of both simple and complex systems, and Petri-Net design techniques for sequential/parallel control systems. Chapters on Hardware Description Language cover the widely-used and powerful Verilog HDL in sufficient detail to facilitate the description and verification of FSMs, and FSM based systems, at both the gate and behavioural levels.

Throughout, the text incorporates many real-world examples that demonstrate designs such as data acquisition, a memory tester, and passive serial data monitoring and detection, among others. A useful accompanying CD offers working Verilog software tools for the capture and simulation of design solutions.

With a linear programmed learning format, this book works as a concise guide for the practising digital designer. This book will also be of importance to senior students and postgraduates of electronic engineering, who require design skills for the embedded systems market.

Note: The ebook version does not provide access to the companion files.

Table of contents

  1. Cover Page
  2. Title Page
  3. Copyright
  4. Contents
  5. Preface
  6. Acknowledgements
  7. 1: Introduction to Finite-State Machines and State Diagrams for the Design of Electronic Circuits and Systems
    1. 1.1 INTRODUCTION
    2. 1.2 LEARNING MATERIAL
    3. 1.3 SUMMARY
  8. 2: Using State Diagrams to Control External Hardware Subsystems
    1. 2.1 INTRODUCTION
    2. 2.2 LEARNING MATERIAL
    3. 2.3 SUMMARY
  9. 3: Synthesizing Hardware from a State Diagram
    1. 3.1 INTRODUCTION TO FINITE-STATE MACHINE SYNTHESIS
    2. 3.2 LEARNING MATERIAL
    3. 3.3 SUMMARY
  10. 4: Synchronous Finite-State Machine Designs
    1. 4.1 TRADITIONAL STATE DIAGRAM SYNTHESIS METHOD
    2. 4.2 DEALING WITH UNUSED STATES
    3. 4.3 DEVELOPMENT OF A HIGH/LOW ALARM INDICATOR SYSTEM
    4. 4.4 SIMPLE WAVEFORM GENERATOR
    5. 4.5 THE DICE GAME
    6. 4.6 BINARY DATA SERIAL TRANSMITTER
    7. 4.7 DEVELOPMENT OF A SERIAL ASYNCHRONOUS RECEIVER
    8. 4.8 ADDING PARITY DETECTION TO THE SERIAL RECEIVER SYSTEM
    9. 4.9 AN ASYNCHRONOUS SERIAL TRANSMITTER SYSTEM
    10. 4.10 CLOCKED WATCHDOG TIMER
    11. 4.11 SUMMARY
  11. 5: The One Hot Technique in Finite-State Machine Design
    1. 5.1 THE ONE HOT TECHNIQUE
    2. 5.2 A DATA ACQUISITION SYSTEM
    3. 5.3 A SHARED MEMORY SYSTEM
    4. 5.4 FAST WAVEFORM SYNTHESIZER
    5. 5.5 CONTROLLING THE FINITE-STATE MACHINE FROM A MICROPROCESSOR/MICROCONTROLLER
    6. 5.6 A MEMORY-CHIP TESTER
    7. 5.7 COMPARING ONE HOT WITH THE MORE CONVENTIONAL DESIGN METHOD OF CHAPTER 4
    8. 5.8 A DYNAMIC MEMORY ACCESS CONTROLLER
    9. 5.9 HOW TO CONTROL THE DYNAMIC MEMORY ACCESS FROM A MICROPROCESSOR
    10. 5.10 DETECTING SEQUENTIAL BINARY SEQUENCES USING A FINITE-STATE MACHINE
    11. 5.11 SUMMARY
  12. 6: Introduction to Verilog HDL
    1. 6.1 A BRIEF BACKGROUND TO HARDWARE DESCRIPTION LANGUAGES
    2. 6.2 HARDWARE MODELLING WITH VERILOG HDL: THE MODULE
    3. 6.3 MODULES WITHIN MODULES: CREATING HIERARCHY
    4. 6.4 VERILOG HDL SIMULATION: A COMPLETE EXAMPLE
    5. REFERENCES
  13. 7: Elements of Verilog HDL
    1. 7.1 BUILT-IN PRIMITIVES AND TYPES
    2. 7.2 OPERATORS AND EXPRESSIONS
    3. 7.3 EXAMPLE ILLUSTRATING THE USE OF VERILOG HDL OPERATORS: HAMMING CODE ENCODER
    4. REFERENCES
  14. 8: Describing Combinational and Sequential Logic using Verilog HDL
    1. 8.1 THE DATA-FLOW STYLE OF DESCRIPTION: REVIEW OF THE CONTINUOUS ASSIGNMENT
    2. 8.2 THE BEHAVIOURAL STYLE OF DESCRIPTION: THE SEQUENTIAL BLOCK
    3. 8.3 ASSIGNMENTS WITHIN SEQUENTIAL BLOCKS: BLOCKING AND NONBLOCKING
    4. 8.4 DESCRIBING COMBINATIONAL LOGIC USING A SEQUENTIAL BLOCK
    5. 8.5 DESCRIBING SEQUENTIAL LOGIC USING A SEQUENTIAL BLOCK
    6. 8.6 DESCRIBING MEMORIES
    7. 8.7 DESCRIBING FINITE-STATE MACHINES
    8. REFERENCES
  15. 9: Asynchronous Finite-State Machines
    1. 9.1 INTRODUCTION
    2. 9.2 DEVELOPMENT OF EVENT-DRIVEN LOGIC
    3. 9.3 USING THE SEQUENTIAL EQUATION TO SYNTHESIZE AN EVENT FINITE-STATE MACHINE
    4. 9.4 IMPLEMENTING THE DESIGN USING SUM OF PRODUCT AS USED IN A PROGRAMMABLE LOGIC DEVICE
    5. 9.5 DEVELOPMENT OF AN EVENT VERSION OF THE SINGLE-PULSE GENERATOR WITH MEMORY FINITE-STATE MACHINE
    6. 9.6 ANOTHER EVENT FINITE-STATE MACHINE DESIGN FROM SPECIFICATION THROUGH TO SIMULATION
    7. 9.7 THE HOVER MOWER FINITE-STATE MACHINE
    8. 9.8 AN EXAMPLE WITH A TRANSITION WITHOUT ANY INPUT
    9. 9.9 UNUSUAL EXAMPLE: RESPONDING TO A MICROPROCESSOR-ADDRESSED LOCATION
    10. 9.10 AN EXAMPLE THAT USES A MEALY OUTPUT
    11. 9.11 AN EXAMPLE USING A RELAY CIRCUIT
    12. 9.12 RACE CONDITIONS IN AN EVENT FINITE-STATE MACHINE
    13. 9.13 WAIT-STATE GENERATOR FOR A MICROPROCESSOR SYSTEM
    14. 9.14 DEVELOPMENT OF AN ASYNCHRONOUS FINITE-STATE MACHINE FOR A CLOTHES SPINNER SYSTEM
    15. 9.15 CAUTION WHEN USING TWO-WAY BRANCHES
    16. 9.16 SUMMARY
    17. REFERENCES
  16. 10: Introduction to Petri Nets
    1. 10.1 INTRODUCTION TO SIMPLE PETRI NETS
    2. 10.2 SIMPLE SEQUENTIAL EXAMPLE USING A PETRI NET
    3. 10.3 PARALLEL PETRI NETS
    4. 10.4 SYNCHRONIZING FLOW IN A PARALLEL PETRI NET
    5. 10.5 SYNCHRONIZATION OF TWO PETRI NETS USING ENABLING AND DISABLING ARCS
    6. 10.6 CONTROL OF A SHARED RESOURCE
    7. 10.7 A SERIAL RECEIVER OF BINARY DATA
    8. 10.8 SUMMARY
    9. REFERENCE
  17. Appendix A: Logic Gates and Boolean Algebra Used in the Book
    1. A.1 BASIC GATE SYMBOLS USED IN THE BOOK WITH BOOLEAN EQUATIONS
    2. A.2 THE EXCLUSIVE OR AND EXCLUSIVE NOR
    3. A.3 LAWS OF BOOLEAN ALGEBRA
    4. A.4 EXAMPLES OF APPLYING THE LAWS OF BOOLEAN ALGEBRA
    5. A.5 SUMMARY
  18. Appendix B: Counting and Shifting Circuit Techniques
    1. B.1 BASIC UP AND DOWN SYNCHRONOUS BINARY COUNTER DEVELOPMENT
    2. B.2 EXAMPLE FOR A 4-BIT SYNCHRONOUS UP-COUNTER USING T-TYPE FLIP-FLOPS
    3. B.3 PARALLEL-LOADING COUNTERS: USING T FLIP-FLOPS
    4. B.4 USING D FLIP-FLOPS TO BUILD PARALLEL-LOADING COUNTERS WITH CHEAP PROGRAMMABLE LOGIC DEVICES
    5. B.5 SIMPLE BINARY UP-COUNTER: WITH PARALLEL INPUTS
    6. B.6 CLOCK CIRCUIT TO DRIVE THE COUNTER (AND FINITE-STATE MACHINES)
    7. B.7 COUNTER DESIGN USING DON'T CARE STATES
    8. B.8 SHIFT REGISTERS
    9. B.9 ASYNCHRONOUS RECEIVER DETAILS OF CHAPTER 4
    10. B.10 SUMMARY
  19. Appendix C: Tutorial on the Use of Verilog HDL to Simulate a Finite-State Machine Design
    1. C.1 INTRODUCTION
    2. C.2 THE SINGLE PULSE WITH MEMORY SYNCHRONOUS FINITE-STATE MACHINE DESIGN: USING VERILOG HDL TO SIMULATE
    3. C.3 TEST-BENCH MODULE AND ITS PURPOSE
    4. C.4 USING SYNAPTICAD'S VERILOGGER EXTREME SIMULATOR
    5. C.5 SUMMARY
  20. Appendix D: Implementing State Machines using Verilog Behavioural Mode
    1. D.1 INTRODUCTION
    2. D.2 THE SINGLE-PULSE/MULTIPLE-PULSE GENERATOR WITH MEMORY FINITE-STATE MACHINE REVISITED
    3. D.3 THE MEMORY TESTER FINITE-STATE MACHINE IN SECTION 5.6
    4. D.4 SUMMARY
  21. Index

Product information

  • Title: FSM-based Digital Design using Verilog HDL
  • Author(s): Peter Minns, Ian Elliott
  • Release date: May 2008
  • Publisher(s): Wiley
  • ISBN: 9780470060704