Book description
As digital circuit elements decrease in physical size, resulting in increasingly complex systems, a basic logic model that can be used in the control and design of a range of semiconductor devices is vital. Finite State Machines (FSM) have numerous advantages; they can be applied to many areas (including motor control, and signal and serial data identification to name a few) and they use less logic than their alternatives, leading to the development of faster digital hardware systems.
This clear and logical book presents a range of novel techniques for the rapid and reliable design of digital systems using FSMs, detailing exactly how and where they can be implemented. With a practical approach, it covers synchronous and asynchronous FSMs in the design of both simple and complex systems, and PetriNet design techniques for sequential/parallel control systems. Chapters on Hardware Description Language cover the widelyused and powerful Verilog HDL in sufficient detail to facilitate the description and verification of FSMs, and FSM based systems, at both the gate and behavioural levels.
Throughout, the text incorporates many realworld examples that demonstrate designs such as data acquisition, a memory tester, and passive serial data monitoring and detection, among others. A useful accompanying CD offers working Verilog software tools for the capture and simulation of design solutions.
With a linear programmed learning format, this book works as a concise guide for the practising digital designer. This book will also be of importance to senior students and postgraduates of electronic engineering, who require design skills for the embedded systems market.
Note: The ebook version does not provide access to the companion files.
Table of contents
 Cover Page
 Title Page
 Copyright
 Contents
 Preface
 Acknowledgements
 1: Introduction to FiniteState Machines and State Diagrams for the Design of Electronic Circuits and Systems
 2: Using State Diagrams to Control External Hardware Subsystems
 3: Synthesizing Hardware from a State Diagram

4: Synchronous FiniteState Machine Designs
 4.1 TRADITIONAL STATE DIAGRAM SYNTHESIS METHOD
 4.2 DEALING WITH UNUSED STATES
 4.3 DEVELOPMENT OF A HIGH/LOW ALARM INDICATOR SYSTEM
 4.4 SIMPLE WAVEFORM GENERATOR
 4.5 THE DICE GAME
 4.6 BINARY DATA SERIAL TRANSMITTER
 4.7 DEVELOPMENT OF A SERIAL ASYNCHRONOUS RECEIVER
 4.8 ADDING PARITY DETECTION TO THE SERIAL RECEIVER SYSTEM
 4.9 AN ASYNCHRONOUS SERIAL TRANSMITTER SYSTEM
 4.10 CLOCKED WATCHDOG TIMER
 4.11 SUMMARY

5: The One Hot Technique in FiniteState Machine Design
 5.1 THE ONE HOT TECHNIQUE
 5.2 A DATA ACQUISITION SYSTEM
 5.3 A SHARED MEMORY SYSTEM
 5.4 FAST WAVEFORM SYNTHESIZER
 5.5 CONTROLLING THE FINITESTATE MACHINE FROM A MICROPROCESSOR/MICROCONTROLLER
 5.6 A MEMORYCHIP TESTER
 5.7 COMPARING ONE HOT WITH THE MORE CONVENTIONAL DESIGN METHOD OF CHAPTER 4
 5.8 A DYNAMIC MEMORY ACCESS CONTROLLER
 5.9 HOW TO CONTROL THE DYNAMIC MEMORY ACCESS FROM A MICROPROCESSOR
 5.10 DETECTING SEQUENTIAL BINARY SEQUENCES USING A FINITESTATE MACHINE
 5.11 SUMMARY
 6: Introduction to Verilog HDL
 7: Elements of Verilog HDL

8: Describing Combinational and Sequential Logic using Verilog HDL
 8.1 THE DATAFLOW STYLE OF DESCRIPTION: REVIEW OF THE CONTINUOUS ASSIGNMENT
 8.2 THE BEHAVIOURAL STYLE OF DESCRIPTION: THE SEQUENTIAL BLOCK
 8.3 ASSIGNMENTS WITHIN SEQUENTIAL BLOCKS: BLOCKING AND NONBLOCKING
 8.4 DESCRIBING COMBINATIONAL LOGIC USING A SEQUENTIAL BLOCK
 8.5 DESCRIBING SEQUENTIAL LOGIC USING A SEQUENTIAL BLOCK
 8.6 DESCRIBING MEMORIES
 8.7 DESCRIBING FINITESTATE MACHINES
 REFERENCES

9: Asynchronous FiniteState Machines
 9.1 INTRODUCTION
 9.2 DEVELOPMENT OF EVENTDRIVEN LOGIC
 9.3 USING THE SEQUENTIAL EQUATION TO SYNTHESIZE AN EVENT FINITESTATE MACHINE
 9.4 IMPLEMENTING THE DESIGN USING SUM OF PRODUCT AS USED IN A PROGRAMMABLE LOGIC DEVICE
 9.5 DEVELOPMENT OF AN EVENT VERSION OF THE SINGLEPULSE GENERATOR WITH MEMORY FINITESTATE MACHINE
 9.6 ANOTHER EVENT FINITESTATE MACHINE DESIGN FROM SPECIFICATION THROUGH TO SIMULATION
 9.7 THE HOVER MOWER FINITESTATE MACHINE
 9.8 AN EXAMPLE WITH A TRANSITION WITHOUT ANY INPUT
 9.9 UNUSUAL EXAMPLE: RESPONDING TO A MICROPROCESSORADDRESSED LOCATION
 9.10 AN EXAMPLE THAT USES A MEALY OUTPUT
 9.11 AN EXAMPLE USING A RELAY CIRCUIT
 9.12 RACE CONDITIONS IN AN EVENT FINITESTATE MACHINE
 9.13 WAITSTATE GENERATOR FOR A MICROPROCESSOR SYSTEM
 9.14 DEVELOPMENT OF AN ASYNCHRONOUS FINITESTATE MACHINE FOR A CLOTHES SPINNER SYSTEM
 9.15 CAUTION WHEN USING TWOWAY BRANCHES
 9.16 SUMMARY
 REFERENCES

10: Introduction to Petri Nets
 10.1 INTRODUCTION TO SIMPLE PETRI NETS
 10.2 SIMPLE SEQUENTIAL EXAMPLE USING A PETRI NET
 10.3 PARALLEL PETRI NETS
 10.4 SYNCHRONIZING FLOW IN A PARALLEL PETRI NET
 10.5 SYNCHRONIZATION OF TWO PETRI NETS USING ENABLING AND DISABLING ARCS
 10.6 CONTROL OF A SHARED RESOURCE
 10.7 A SERIAL RECEIVER OF BINARY DATA
 10.8 SUMMARY
 REFERENCE
 Appendix A: Logic Gates and Boolean Algebra Used in the Book

Appendix B: Counting and Shifting Circuit Techniques
 B.1 BASIC UP AND DOWN SYNCHRONOUS BINARY COUNTER DEVELOPMENT
 B.2 EXAMPLE FOR A 4BIT SYNCHRONOUS UPCOUNTER USING TTYPE FLIPFLOPS
 B.3 PARALLELLOADING COUNTERS: USING T FLIPFLOPS
 B.4 USING D FLIPFLOPS TO BUILD PARALLELLOADING COUNTERS WITH CHEAP PROGRAMMABLE LOGIC DEVICES
 B.5 SIMPLE BINARY UPCOUNTER: WITH PARALLEL INPUTS
 B.6 CLOCK CIRCUIT TO DRIVE THE COUNTER (AND FINITESTATE MACHINES)
 B.7 COUNTER DESIGN USING DON'T CARE STATES
 B.8 SHIFT REGISTERS
 B.9 ASYNCHRONOUS RECEIVER DETAILS OF CHAPTER 4
 B.10 SUMMARY
 Appendix C: Tutorial on the Use of Verilog HDL to Simulate a FiniteState Machine Design
 Appendix D: Implementing State Machines using Verilog Behavioural Mode
 Index
Product information
 Title: FSMbased Digital Design using Verilog HDL
 Author(s):
 Release date: May 2008
 Publisher(s): Wiley
 ISBN: 9780470060704
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