book

FSM-based Digital Design using Verilog HDL

Name: FSM-based Digital Design using Verilog HDL
ISBN: 9780470060704

by Peter Minns, Ian Elliott

May 2008

Intermediate to advanced

408 pages

11h 8m

English

Wiley

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Cover Page
Title Page
Copyright
Contents
Preface
Acknowledgements
1: Introduction to Finite-State Machines and State Diagrams for the Design of Electronic Circuits and Systems
1.1 INTRODUCTION1.2 LEARNING MATERIAL1.3 SUMMARY
2: Using State Diagrams to Control External Hardware Subsystems
2.1 INTRODUCTION2.2 LEARNING MATERIAL2.3 SUMMARY
3: Synthesizing Hardware from a State Diagram
3.1 INTRODUCTION TO FINITE-STATE MACHINE SYNTHESIS3.2 LEARNING MATERIAL3.3 SUMMARY
4: Synchronous Finite-State Machine Designs
4.1 TRADITIONAL STATE DIAGRAM SYNTHESIS METHOD4.2 DEALING WITH UNUSED STATES4.3 DEVELOPMENT OF A HIGH/LOW ALARM INDICATOR SYSTEM4.4 SIMPLE WAVEFORM GENERATOR4.5 THE DICE GAME4.6 BINARY DATA SERIAL TRANSMITTER4.7 DEVELOPMENT OF A SERIAL ASYNCHRONOUS RECEIVER4.8 ADDING PARITY DETECTION TO THE SERIAL RECEIVER SYSTEM4.9 AN ASYNCHRONOUS SERIAL TRANSMITTER SYSTEM4.10 CLOCKED WATCHDOG TIMER4.11 SUMMARY

5: The One Hot Technique in Finite-State Machine Design
5.1 THE ONE HOT TECHNIQUE5.2 A DATA ACQUISITION SYSTEM5.3 A SHARED MEMORY SYSTEM5.4 FAST WAVEFORM SYNTHESIZER5.5 CONTROLLING THE FINITE-STATE MACHINE FROM A MICROPROCESSOR/MICROCONTROLLER5.6 A MEMORY-CHIP TESTER5.7 COMPARING ONE HOT WITH THE MORE CONVENTIONAL DESIGN METHOD OF CHAPTER 45.8 A DYNAMIC MEMORY ACCESS CONTROLLER5.9 HOW TO CONTROL THE DYNAMIC MEMORY ACCESS FROM A MICROPROCESSOR5.10 DETECTING SEQUENTIAL BINARY SEQUENCES USING A FINITE-STATE MACHINE5.11 SUMMARY
6: Introduction to Verilog HDL
6.1 A BRIEF BACKGROUND TO HARDWARE DESCRIPTION LANGUAGES6.2 HARDWARE MODELLING WITH VERILOG HDL: THE MODULE6.3 MODULES WITHIN MODULES: CREATING HIERARCHY6.4 VERILOG HDL SIMULATION: A COMPLETE EXAMPLEREFERENCES
7: Elements of Verilog HDL
7.1 BUILT-IN PRIMITIVES AND TYPES7.2 OPERATORS AND EXPRESSIONS7.3 EXAMPLE ILLUSTRATING THE USE OF VERILOG HDL OPERATORS: HAMMING CODE ENCODERREFERENCES
8: Describing Combinational and Sequential Logic using Verilog HDL
8.1 THE DATA-FLOW STYLE OF DESCRIPTION: REVIEW OF THE CONTINUOUS ASSIGNMENT8.2 THE BEHAVIOURAL STYLE OF DESCRIPTION: THE SEQUENTIAL BLOCK8.3 ASSIGNMENTS WITHIN SEQUENTIAL BLOCKS: BLOCKING AND NONBLOCKING8.4 DESCRIBING COMBINATIONAL LOGIC USING A SEQUENTIAL BLOCK8.5 DESCRIBING SEQUENTIAL LOGIC USING A SEQUENTIAL BLOCK8.6 DESCRIBING MEMORIES8.7 DESCRIBING FINITE-STATE MACHINESREFERENCES
9: Asynchronous Finite-State Machines
9.1 INTRODUCTION9.2 DEVELOPMENT OF EVENT-DRIVEN LOGIC9.3 USING THE SEQUENTIAL EQUATION TO SYNTHESIZE AN EVENT FINITE-STATE MACHINE9.4 IMPLEMENTING THE DESIGN USING SUM OF PRODUCT AS USED IN A PROGRAMMABLE LOGIC DEVICE9.5 DEVELOPMENT OF AN EVENT VERSION OF THE SINGLE-PULSE GENERATOR WITH MEMORY FINITE-STATE MACHINE9.6 ANOTHER EVENT FINITE-STATE MACHINE DESIGN FROM SPECIFICATION THROUGH TO SIMULATION9.7 THE HOVER MOWER FINITE-STATE MACHINE9.8 AN EXAMPLE WITH A TRANSITION WITHOUT ANY INPUT9.9 UNUSUAL EXAMPLE: RESPONDING TO A MICROPROCESSOR-ADDRESSED LOCATION9.10 AN EXAMPLE THAT USES A MEALY OUTPUT9.11 AN EXAMPLE USING A RELAY CIRCUIT9.12 RACE CONDITIONS IN AN EVENT FINITE-STATE MACHINE9.13 WAIT-STATE GENERATOR FOR A MICROPROCESSOR SYSTEM9.14 DEVELOPMENT OF AN ASYNCHRONOUS FINITE-STATE MACHINE FOR A CLOTHES SPINNER SYSTEM9.15 CAUTION WHEN USING TWO-WAY BRANCHES9.16 SUMMARYREFERENCES
10: Introduction to Petri Nets
10.1 INTRODUCTION TO SIMPLE PETRI NETS10.2 SIMPLE SEQUENTIAL EXAMPLE USING A PETRI NET10.3 PARALLEL PETRI NETS10.4 SYNCHRONIZING FLOW IN A PARALLEL PETRI NET10.5 SYNCHRONIZATION OF TWO PETRI NETS USING ENABLING AND DISABLING ARCS10.6 CONTROL OF A SHARED RESOURCE10.7 A SERIAL RECEIVER OF BINARY DATA10.8 SUMMARYREFERENCE
Appendix A: Logic Gates and Boolean Algebra Used in the Book
A.1 BASIC GATE SYMBOLS USED IN THE BOOK WITH BOOLEAN EQUATIONSA.2 THE EXCLUSIVE OR AND EXCLUSIVE NORA.3 LAWS OF BOOLEAN ALGEBRAA.4 EXAMPLES OF APPLYING THE LAWS OF BOOLEAN ALGEBRAA.5 SUMMARY
Appendix B: Counting and Shifting Circuit Techniques
B.1 BASIC UP AND DOWN SYNCHRONOUS BINARY COUNTER DEVELOPMENTB.2 EXAMPLE FOR A 4-BIT SYNCHRONOUS UP-COUNTER USING T-TYPE FLIP-FLOPSB.3 PARALLEL-LOADING COUNTERS: USING T FLIP-FLOPSB.4 USING D FLIP-FLOPS TO BUILD PARALLEL-LOADING COUNTERS WITH CHEAP PROGRAMMABLE LOGIC DEVICESB.5 SIMPLE BINARY UP-COUNTER: WITH PARALLEL INPUTSB.6 CLOCK CIRCUIT TO DRIVE THE COUNTER (AND FINITE-STATE MACHINES)B.7 COUNTER DESIGN USING DON'T CARE STATESB.8 SHIFT REGISTERSB.9 ASYNCHRONOUS RECEIVER DETAILS OF CHAPTER 4B.10 SUMMARY
Appendix C: Tutorial on the Use of Verilog HDL to Simulate a Finite-State Machine Design
C.1 INTRODUCTIONC.2 THE SINGLE PULSE WITH MEMORY SYNCHRONOUS FINITE-STATE MACHINE DESIGN: USING VERILOG HDL TO SIMULATEC.3 TEST-BENCH MODULE AND ITS PURPOSEC.4 USING SYNAPTICAD'S VERILOGGER EXTREME SIMULATORC.5 SUMMARY
Appendix D: Implementing State Machines using Verilog Behavioural Mode
D.1 INTRODUCTIOND.2 THE SINGLE-PULSE/MULTIPLE-PULSE GENERATOR WITH MEMORY FINITE-STATE MACHINE REVISITEDD.3 THE MEMORY TESTER FINITE-STATE MACHINE IN SECTION 5.6D.4 SUMMARY
Index

Content preview from FSM-based Digital Design using Verilog HDL

Index

$readmemb – system function 237

$readmemh – system function 237

$signed() – system function 178

$unsigned() – system function 178

@(event_expression) statement 220

Active low output signals 14, 64, 65

Address activated FSM control 291

Address activated FSM control state diagram 292

always block 199

Arithmetic right-shift () 178

Arrays of reg's 231

assign parallel statement 148

Asynchronous FSM 267

important note 280

Asynchronous FSM to relay circuit 296, 299

Asynchronous FSM using more than two event cells 305

Asynchronous Petri net structure 317

Asynchronous receiver block diagram 90, 94, 331, 359

Asynchronous receiver complete system simulation 358-365

Asynchronous receiver Protocol 89, 93

Asynchronous reset 54, 58, 221

Asynchronous serial receiver 88

Asynchronous serial receiver block diagram 90, 97, 359

Asynchronous serial receiver simulation 96, 365

Asynchronous serial receiver state diagram 91

Asynchronous serial receiver with parity 92

Asynchronous serial receiver with parity state diagram 95

Asynchronous serial transmitter 95

Asynchronous serial transmitter simulation 99

Asynchronous state diagrams without inputs along transitions 290

Asynchronous transmitter 95

Asynchronous transmitter state diagram 98

Base (number) 169

Basic logic gate symbols 337

begin..end block 199

Behavioural Asynchronous (event) FSM development 379

Bi-directional port 178

Binary counters using ...

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FSM-based Digital Design using Verilog HDL

by Peter Minns, Ian Elliott

Index

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