This appendix quickly describes an FSM model in Verilog code and then simulates it using SynaptiCAD's VeriLogger Extreme simulator. The code for the model, VeriLogger Extreme, and the code for most of the examples in the book are contained on the CDROM provided with the book.
The design of a single-pulse generator with memory is outlined and then a Verilog HDL file is created. This Verilog file will use the most basic of the Verilog methods so as to keep it simple.
Whenever input s is asserted high, a single pulse is to be generated at the output P. Signal s must be returned low and then reasserted high again before another pulse can be generated. In addition, a memory output L is to go high to indicate that a pulse has been generated; going low again when the s input is returned to logic 0.
Figure C.1 illustrates the block diagram of the system.
A state diagram is implemented as illustrated in Figure C.2.