Low-Voltage SOI CMOS VLSI Devices and Circuits

Contents

Preface

Acknowledgments

1 Introduction

1.1 Evolution of CMOS VLSI

1.2 SOI versus Bulk

1.3 Low-Voltage SOI VLSI

1.4 Objectives

References

2 SOI CMOS Devices-Part I

2.1 Basic SOI Technology

2.1.1 SOI Wafers

2.1.2 Shallow Trench Isolation

2.1.3 SOI Device Structure

2.2 Back Gate Bias Effects

2.2.1 PD versus FD

2.2.2 Inversion versus Accumulation

2.3 Short Channel Effects

2.3.1 Biasing Dependence

2.3.2 Structure Dependence

2.3.3 Processing Dependence

2.3.4 Subthreshold

2.4 Narrow Channel Effects

2.4.1 Structure Dependence

2.4.2 Subthreshold

2.4.3 Back Gate Bias Dependence

2.4.4 Isolation Dependence

2.5 Mobility

2.5.1 Vertical Field Dependence

2.5.2 Lateral Field Dependence

2.6 Floating Body Effects

2.6.1 Strong Inversion Kink Effects

2.6.2 Body Contact

2.6.3 Various Techniques to Reduce Kink Effects

2.7 Subthreshold Behavior

2.7.1 FD versus PD

2.7.2 PD

2.7.3 DIBL Dependence

2.7.4 Latch/GIDL Behavior

2.8 Impact Ionization

2.8.1 Basic Analysis

2.8.2 Body Current

2.8.3 Monitoring Techniques

2.9 Breakdown

2.9.1 Structure Dependence

2.9.2 Bipolar Induced Effects

2.9.3 LDD

2.10 Transient-Induced Leakage

2.11 History Effects

2.12 Self-Heating

2.12.1 Drain Current

2.12.2 Thermal Resistance

2.12.3 Thermal Coupling

2.12.4 AC Behavior

2.13 Transient Behaviors

2.13.1 Floating-Body Induced

2.13.2 History Effect

2.14 Summary

References

Problems

3 SOI CMOS Devices-Part II

3.1 Hot Carriers

3.1.1 NMOS

3.1.2 PMOS

3.1.3 Substrate Current

3.1.4 Back Gate Bias

3.1.5 Device Structure Dependence ...