April 2016
Intermediate to advanced
546 pages
12h 41m
English
Symbol |
Description |
|---|---|
— |
Not changed |
x |
Updated according to data |
? |
Undefined |
0 |
Reset to 0 |
1 |
Set to 1 |
3 |
c|=(msn>9) |
4 |
Most significant bit of b |
5 |
Set when interrupt occurs; if previously set, a nonmaskable interrupt is required to exit the wait state |
TABLE A8.2HC11 Instruction Set



Note: Accumulator A and B are → bits. Register D (a = MSB; b = LSB), X, and Y are 1 6 bits. ...
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