Multicore DSP

6The TMS320C66x interrupts

CHAPTER MENU

1. 6.1 Introduction
   1. 6.1.1 Chip‐level interrupt controller
2. 6.2 The interrupt controller
3. 6.3 Laboratory experiment
   1. 6.3.1 Experiment 1: Using the GIPIOs to trigger some functions
   2. 6.3.2 Experiment 2: Using the console to trigger an interrupt
4. 6.4 Conclusion
5. References

6.1 Introduction

As with most microprocessors, the TMS320C66x allows normal program flow to be interrupted. In response to the interruption, the CPU finishes executing the current instruction(s) and branches to a procedure which services the interrupt. To service an interrupt, the user or the system must save the contents of the registers and the context of the current process, then service the interrupt task, restore the registers and the context of the process, and finally resume the original process (see Figure 6.1). The interrupt can come from an external device, an internal peripheral or simply a special instruction in the program.

Figure 6.1 Interrupt response procedure.

There are four types of interrupts on the TMS320CC66x CPUs. These are the two non‐maskable interrupts (Reset and NMI) and maskable interrupts (EXCEP and INT4–INT15) (see Figure 6.2 and Table 6.1). The interrupt controllers described in this chapter allow events to be mapped to any of the input interrupts from INT4 to INT15.

Figure 6.2 Various interrupts available.

Table 6.1 Interrupt sources ...