Multicore DSP

14Multicore Navigator

CHAPTER MENU

1. 14.1 Introduction
2. 14.2 Navigator architecture
   1. 14.2.1 The PKDMA
      1. 14.2.1.1 PKDMA transmit side
      2. 14.2.1.2 PKDMA receive side
      3. 14.2.1.3 Infrastructure PKDMA
   2. 14.2.2 Descriptors
      1. 14.2.2.1 Host packet descriptors
      2. 14.2.2.2 Monolithic packet descriptor
      3. 14.2.2.3 Setting up the memory regions for the descriptors
   3. 14.2.3 Queue Manager Subsystem
   4. 14.2.4 Queue Manager
      1. 14.2.4.1 Queue peek registers
      2. 14.2.4.2 Link RAM
   5. 14.2.5 Accumulator packet data structure processors
      1. 14.2.5.1 Accumulation
      2. 14.2.5.2 Quality of service
      3. 14.2.5.3 Event management (resource sharing and job load balancing)
   6. 14.2.6 Interrupt distributor module
3. 14.3 Complete functionality of the Navigator
4. 14.4 Laboratory experiment
5. 14.5 Conclusion
6. References

14.1 Introduction

The Multicore Navigator, also referred to as simply the Navigator, provides a high‐speed packet data transfer to enhance CorePac to accelerator/peripheral data movements, core‐to‐core data movements, inter‐core communication and synchronisation without loading the CorePacs. To achieve this, the Navigator architecture is built with two main components, the hardware Queue Manager Subsystem (QMSS) and the Packet DMA engine (PKDMA) which is similar to the EDMA (Enhanced Direct Memory Access) engine covered in Chapter 8. Figure 14.1 and Figure 14.2 show the locations of the Navigators for both the KeyStone I and the KeyStone II, respectively.

Figure 14.1 Functional block diagram for the C6678 [1].

Figure 14.2 Functional ...