Appendix D. SPU Instruction Set Reference
Chapter 15, “SPU Assembly Language,” presented SPU assembly coding in depth, but there wasn’t enough room to add details related to the timing and pipeline usage of the individual instructions. In this case, pipeline usage refers to whether the instruction is processed by the even pipeline (0) or the odd pipeline (1). This is important to know; the SPU can issue two instructions in the same cycle if they are processed by different pipelines.
This appendix lists the SPU’s instructions in alphabetic order. Each entry shows the number of clock cycles required by the instruction (latency), which pipeline it uses (0 or 1), and a description of the instruction’s purpose.
Table D.1. SPU Load/Store Instructions ...
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