The Definitive Guide to ARM® Cortex®-M3 and Cortex®-M4 Processors, 3rd Edition

Chapter 4

Architecture

Abstract

Details of the architecture including programmer’s model, core registers, stack operations, overview of the exceptions and interrupts, introduction of Nested Vector Interrupt Controller (NVIC), reset sequence.

Keywords

Architecture; programmer’s model; register bank; special registers; floating point; Program Status Register (PSR); Nested Vector Interrupt Controller (NVIC); System Control Block (SCB); Reset sequence; debug

Chapter Outline

4.1 Introduction to the architecture

4.2 Programmer’s model

4.2.1 Operation modes and states

Operation states

Operation modes

4.2.2 Registers

R0 – R12

R13, stack pointer (SP)

R14, link register (LR)

R15, program counter (PC)

Register names in programming

4.2.3 Special registers ...