Computers as Components, 2nd Edition

282 CHAPTER 5 Program Design and Analysis

counter. The receiver sample interrupt handler is a natural candidate to double as

the receiver timer since the receiver’s time points are relative to samples.

The hardware architecture is relatively simple. In addition to the analog/digital

and digital/analog converters, a timer is required. The amount of memory required

to implement the algorithms is relatively small.

5.11.4 Component Design and Testing

The transmitter and receiver can be tested relatively thoroughly on the host platform

since the timing-critical code only delivers data samples. The transmitter’s output

is relatively easy to verify, particularly ...