Computers as Components, 2nd Edition

4.1 The CPU Bus 165

Fast address

enable and fast

write/slow adrs,

slow write

Fast address

enable and fast

read/slow adrs,

slow read

Fast address

enable

Slow ack/fast ack

Slow data/fast data, fast ack

Fast data/

slow data

Slow ack

Slow ack

Slow ack

Bridge

Idle

Read

adrs

Read

data

Write

adrs

Write

data

Fast address

enable

Fast

read/write

Fast adrs

Fast data

Fast ack

Fast bus

(slave)

Slow address

enable

Slow

read/write

Slow adrs

Slow data

Slow ack

Slow bus

(master)

FIGURE 4.13

UML state diagram of bus bridge operation.

be overlapped as much as possible to reduce the latency of bus-to-bus transfers.

Similarly, the bottom sequence of states reads from the slow bus and writes the data

to the fast ...