July 2008
Intermediate to advanced
544 pages
16h 52m
English
Content preview from Computers as Components, 2nd Edition
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390 CHAPTER 7 Multiprocessors
PE
0
PE
1
PE
2
PE
15
Comparator
Address generator
Search area
Network Network
Network
control
Macroblock
Motion
vector
FIGURE 7.31
An architecture for the motion estimation accelerator [Dut96].
Based on our understanding of efficient architectures for accelerating motion
estimation, we can derive a more detailed definition of the architecture in UML,
which is shown in Figure 7.33. The system includes the two memories for pixels,
one a single-port memory and the other dual ported. A bus interface module is
responsible for communicating with the PCI bus and the rest of the system. The
estimation engine reads pixels from the M and S memor