July 2008
Intermediate to advanced
544 pages
16h 52m
English
Content preview from Computers as Components, 2nd Edition
Become an O’Reilly member and get unlimited access to this title plus top books and audiobooks from O’Reilly and nearly 200 top publishers, thousands of courses curated by job role, 150+ live events each month,
Start your free trial
7.4 Consumer Electronics Architecture 369
But it is not necessary to wait so long for some data. Consider this schedule:
A[0]
B[0]
C[0]
A[1]
B[1]
C[1]
...
This schedule generates the first output after three cycles and generates new outputs every
three cycles thereafter.
Equally important, as we include more components in the transfer, we intro-
duce more opportunities for interr uptions and variations in execution time. Any
resource that is shared may be subject to delays caused by other processes that
use the resource. Buses may handle other transfers; memories may also be shared
among several processors.
7.4 CONSUMER ELECTRONICS ARCHITECTURE
Although some ...