Computers as Components, 2nd Edition

110 CHAPTER 3 CPUs

The worst-case latency to respond to an interrupt includes the following

components:

■ two cycles to synchronize the external request,

■ up to 20 cycles to complete the current instruction,

■ three cycles for data abort, and

■ two cycles to enter the interrupt handling state.

This adds up to 27 clock cycles. The best-case latency is four clock cycles.

Interrupts in C55x Interrupts in the C55x [Tex04] never take less than seven clock

cycles. In many situations, they take 13 clock cycles.

A maskable interrupt is processed in several steps once the interrupt request is

sent to the CPU:

■ The interrupt flag register (IFR) corresponding to ...