Computers as Components, 2nd Edition

4.1 The CPU Bus 159

Clock

R/W

Address

enable

Burst

Address

Data

Data ready

Time

Data 1

Data 2

Data 3

Data 4

FIGURE 4.6

A burst read transaction.

asserted and when it is actually asserted are known as wait states. Wait states are

commonly used to connect slow, inexpensive memories to buses.

We can also use the bus handshaking signals to perform burst transfers,as

illustrated in Figure 4.6. In this burst read transaction, the CPU sends one address

but receives a sequence of data values.We add an extra line to the bus,called burst9

here,which signals when a transaction is actually a burst. Releasing the burst9 signal

tells the device that enough data has been transmitted. ...