Digital System Clocking: High-Performance and Low-Power Aspects

INDEX

Active deskewing, 84. See also Deskewing

Alpha, see Microprocessor

Alpha particles, 204

Asynchronous systems, 4

C²MOS

latch-mux, see Dual-edge-triggered storage element

M-S latch, see Latch

CCFF, see Flip-flop

Circuit sizing, 106

CISC, see Complex instruction set computers

Clock

buffers, 11, 108, 209, 211

conditioning, 216

core clock, 194, 196

cycle, 2

distribution, 8, 19, 119, 187, 198, 209–212

H-tree, 24, 193, 210

X-tree, 24, 210

domains, 198, 210, 217

drivers, see Clock buffers

duty cycle, see Timing parameters

edge degradation, 36

energy, 180

external, 11, 13

frequency, 2

gating, 112, 122, 167–177

global, 112

local, 113

generation, 8, 9, 197

global clock, 193, 210, 221

grid, 24, 194, 196, 201, 209–212

hierarchy, 211

internal, 10, 12

jitter, see Timing parameters

load, 10

low-swing clock, 108, 177, 179

multiple phase, 8

network, see clock distribution

nonoverlapping clocks, 223

on-board, 10

on-chip, 10

optimal width, 69, 77

overlap, 223

phase error, 12, 197

pulsed clock, 199, 221

off-chip reference, 9, 11

on-chip reference, 179, 196

RC matched tree, 24

regenerator, 225

scan port clock, 225

single-phase, 8

skew, see Timing parameters

slope, 61

tree, see Clock distribution

tuning, 18

two-phase, 8, 70, 72

uncertainties, see Timing parameters

width, see Timing parameters

Clocking, 2

dual-edge, 75

edge-sensitive, 36, 64, 91

level sensitive, 91, 98, 213

low-swing, 108

single-phase, 64

soft edge-sensitive, 102

two-phase, 70, 213

Clock-on-demand, see Latch

Combinational logic, ...