Embedded Systems: An Integrated Approach by Pearson

AUTOMATED DESIGN OF DIGITAL ICs 609

Semantic Checks

i) Design entry needs to be checked for language correctness.

ii)  is phase can also be used to check the synthesizability of code, i.e., whether the

code can lead to practical hardware.

iii) It is important to check synthesizability, as the RTL should be mapped to standard

cells using synthesis tools later in the fl ow.

Design Veri cation

i) Verifi cation is the process where the design is tested against the specifi cation.

What do we do with the ‘netlist’ obtained after the front-end design?

 ere are two options.

i) One is to burn it onto an FPGA; thus, the FPGA gets confi gured to act functionally

as per the designed model.

Note Keep in mind that SRAM FPGAs are re-confi gurable. At ...