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Embedded Systems: An Integrated Approach by Pearson

Name: Embedded Systems: An Integrated Approach by Pearson
Author: Lyla B Das
ISBN: 9789332511675

by Lyla B Das

May 2024

Intermediate to advanced

784 pages

26h 59m

English

Pearson India

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Cover (1/2)
Cover (2/2)
Contents (1/2)
Contents (2/2)
Preface (1/2)
Preface (2/2)
About the Author
Part I: Design Aspects of Embedded Systems
Chapter 0: Basics of Computer Architecture and the Binary Number System
0.1 Basics of Computer Architecture0.1.1 The Block Diagram of a Computer0.1.2 The System Bus0.1.3 The Processor0.1.4 System Clock0.1.5 Memory0.1.6 The I/O System
0.2 Computer Languages
0.2.1 Machine Language, Assembly Languageand High Level Language0.2.2 Comparison

0.3 RISC and CISC Architectures
0.4 Number Systems
0.4.1 The Decimal System0.4.2 The Binary Number System
0.4.3 The Hexadecimal Number System
0.5 Number Format Conversions (1/2)0.5.1 Conversion from Decimal to Binary0.5.2 Conversion from Decimal to Hexadecimal0.5.3 Converting from Binary to Hexadecimal0.5.4 BCD Numbers0.5.5 ASCII Code
0.5 Number Format Conversions (2/2)
0.5.6 Representation of Negative Numbers
0.6 Computer Arithmetic (1/2)
0.6.1 Addition of Unsigned Numbers0.6.2 Addition of Packed BCD Numbers0.6.3 Addition of Negative Numbers0.6.4 Subtraction0.6.5 Packed BCD Subtraction
0.6 Computer Arithmetic (2/2)
0.6.6 Subtraction of Signed Numbers0.6.7 Addition of Numbers of Different Lengths
0.7 Units of Memory Capacity
Key Points of this Chapter
Questions
Exercises
Chapter 1: Introduction to Embedded Systems
Introduction
1.1 Application Domain of Embedded Systems
1.2 Desirable Features and General Characteristics of Embedded Systems
1.3 Model of an Embedded System
1.4 Microprocessor vs Microcontroller1.4.1 Microprocessor Unit (MPU)1.4.2 Microcontroller Unit (MCU)
1.5 Example of a Simple Embedded System
1.6 Figures of Merit for an Embedded System
1.7 Classification of MCUs: 4/8/16/32 Bits
1.7.1 ASIC: Application Specific Integrated Circuit1.7.2 FPGA (Field Programmable Gate Array)1.7.3 DSP Processors
1.8 History of Embedded Systems
1.9 Current Trends
ConclusionKey Points of this Chapter
Questions
Exercises
Chapter 2: Embedded Systems—The Hardware Point of View
Introduction
2.1 Microcontroller Unit (MCU)
2.1.1 The Processor2.1.2 The Harvard Architecture
2.2 A Popular 8-bit MCU (1/3)
2.2.1 General Purpose I/O (GPIO)2.2.2 Clock2.2.3 Power on Reset
2.2 A Popular 8-bit MCU (2/3)
2.2.4 Brown Out Reset2.2.5 Timers and Counters2.2.6 Watchdog Timer2.2.7 Real-time Clock (RTC)2.2.8 Stack
2.2 A Popular 8-bit MCU (3/3)
2.2.9 Interrupts2.2.10 DMA2.2.11 Communication Ports
2.3 Memory for Embedded Systems (1/3)
2.3.1 Semiconductor Memory2.3.2 Random Access Memory (RAM)2.3.3 Dynamic RAM (DRAM)
2.3 Memory for Embedded Systems (2/3)
2.3.4 ROM (Read Only Memory)
2.3 Memory for Embedded Systems (3/3)
2.3.5 Caches
2.4 Low Power Design
2.5 Pullup and Pulldown Resistors
2.5.1 Floating State of an Input2.5.2 Pulldown and Pullup Resistances2.5.3 Open Collector/Open Drain Gates2.5.4 Weak and Strong Pullup2.5.5 High Impedance State, Hi-Z
Conclusion
Key Points of this Chapter
Questions
Exercises
Chapter 3: Sensors, ADCs and Actuators
Introduction
3.1 Sensors (1/2)
3.1.1 Temperature Sensors3.1.2 Light Sensors
3.1 Sensors (2/2)
3.1.3 Proximity/Range Sensors3.1.4 Encoders3.1.5 Humidity Sensors3.1.6 Other Sensors
3.2 Analog to Digital Converters (1/2)
3.2.1 ADC Interfacing *
3.2 Analog to Digital Converters (2/2)
3.3 Actuators (1/6)
3.3.1 Displays
3.3 Actuators (2/6)
3.3 Actuators (3/6)
3.3.2 Motors
3.3 Actuators (4/6)
3.3 Actuators (5/6)
3.3.3 Optocouplers/Opto Isolators3.3.4 Relays
3.3 Actuators (6/6)
Conclusion
Key Points of this Chapter
Questions
Exercises
Chapter 4: Examples of Embedded Systems
Introduction4.1 Mobile Phone4.1.1 Block Diagram4.1.2 The Cellular Concept4.1.3 Multiple Access4.1.4 Frequency Re-use4.1.5 Handoff (Handover)4.1.6 Spread Spectrum Techniques
4.1.7 Set Up and Maintanence
4.1.8 Conclusion
4.2 Automotive Electronics
4.2.1 Electronic Fuel Injection (EFI)4.2.2 Anti-lock Braking System (ABS)4.2.3 Electronic Stability Control4.2.4 Adaptive Cruise Control4.2.5 Airbag Deployment4.2.6 Automotive Navigation Systems
4.2.7 Conclusion
4.3 Radio Frequency Identification (RFID)4.3.1 RFID Architecture
4.4 Wireless Sensor Networks (WISENET)
4.4.1 Applications
4.5 Robotics4.5.1 Sensors4.5.2 Actuators4.5.3 Embedded Intelligence4.5.4 Types of Robots4.5.5 Open Loop and Closed Loop Systems4.5.6 Designing an Autonomous Robotic System
4.6 Biomedical Applications
4.7 Brain Machine Interface
4.7.1 Block Diagram4.7.2 Stages of a BMI4.7.3 End Device4.7.4 Important Milestones
Conclusion
Key Points of this ChapterQuestions
Exercises
Chapter 5: Buses and Protocols
Introduction5.1 Defining Buses and Protocols5.1.1 Processor-memory Bus5.1.2 Peripheral Buses5.1.3 Embedded Processors/Microcontrollers5.1.4 Parallel vs Serial Buses
5.1.5 Serial Communications
5.1.6 Bus Arbitration
5.2 On-board Buses for Embedded Systems (1/2)
5.2.1 The I2C Protocol5.2.2 The SPI Bus
5.2 On-board Buses for Embedded Systems (2/2)
5.3 External Buses (1/4)
5.3.1 The USB
5.3 External Buses (2/4)
5.3.2 The Firewire Port5.3.3 The Standard Serial Port
5.3 External Buses (3/4)
5. 3.4 RS 422/RS 4855.3.5 Ethernet
5.3 External Buses (4/4)
5.4 Automotive Buses (1/2)
5.4.1 Controller Area Network (CAN)
5.4 Automotive Buses (2/2)
5.5 Wireless Communications Protocols (1/2)
5.5.1 WLAN (IEEE 802.11)5.5.2 IEEE 802.15 for WPAN
5.5 Wireless Communications Protocols (2/2)
Conclusion
Key Points of this Chapter
Questions
Exercises
Chapter 6: Software Development Tools
Introduction6.1 Embedded Program Development6.1.1 The Initial Steps6.1.2 The Integrated Development Environment6.1.3 Code Editor6.1.4 GUI6.1.5 Compiler6.1.6 Assembler6.1.7 Builder
6.1.8 Disassembly
6.1.9 Linker
6.1.10 Simulator
6.2 Downloading the Hex File to the Non-volatile Memory6.2.1 Out of Circuit Programming6.2.2 In System Programming (ISP)6.2.3 Porting an OS to an Embedded Board6.2.4 Emulator6.2.5 ICE (In-Circuit Emulator)
6.3 Hardware Simulator
Conclusion
Key Points of this ChapterQuestions
Exercises
Part II: Software Design Aspects
Chapter 7: Operating System Concepts
Introduction
7.1 Embedded Operating Systems
7.2 Network Operating Systems (NOS)7.3 Layers of an Operating System
7.4 History of Operating Systems
7.5 Functions Performed by an OS (Components of an OS)
7.5.1 Processor Management7.5.2 Memory Management7.5.3 IO Management7.5.4 File Management7.5.5 Multiprogramming7.5.6 Protection and Security
7.5.7 Network Management
7.6 Some Terms Associated with Operating Systems and Computer Usage7.6.1 Low Level Software Utility7.6.2 Boot Loader7.6.3 User Interface
7.6.4 Application Programming Interface (API)
7.6.5 POSIX7.7 The Kernel7.7.1 Types of Kernels
7.8 Tasks/Processes
7.8.1 Task (Process) Control Block7.8.2 Multitasking7.8.3 Task (Process) Scheduling7.8.4 CPU and IO Bound Tasks7.8.5 Selection of a Scheduling Algorithm
7.8.6 CPU Scheduler and Resource Manager
7.9 Scheduling Algorithms (1/3)7.9.1 Pre-emption7.9.2 Assumptions7.9.3 Non-preemptive Methods of Scheduling7.9.4 Shortest Job Next (SJN)
7.9 Scheduling Algorithms (2/3)
7.9.5 Pre-emeptive Scheduling Strategies
7.9 Scheduling Algorithms (3/3)
7.10 Threads
7.11 Interrrupt Handling
7.11.1 Interrupts and Task Switching
7.12 Inter Process (Task) Communications (IPC)7.12.1 Task/Process Communication Methods
7.13 Task Synchronization (1/2)
7.13.1 Parallelism aka concurrency7.13.2 The Race Condition7.13.3 Critical Section7.13.4 The Readers ‘Writers’ Problem
7.13 Task Synchronization (2/2)
7.13.5 Deadlocks
7.14 Semaphores
7.14.1 Binary Semaphores7.14.2 Counting Semaphores
7.14.3 Binary Semaphore vs Mutex
7.15 Priority Inversion7.15.1 Solutions
7.16 Device Drivers
7.16.1 Reading a Key Pressed Using a Keyboard Driver7.16.2 Purpose of a Device Driver7.16.3 Device Driver Design
7.17 Codes/Pseudo Codes for OS Functions (1/3)
7.17.1 Multitasking
7.17 Codes/Pseudo Codes for OS Functions (2/3)
7.17.2 Mutex, Semaphore and Mailbox
7.17 Codes/Pseudo Codes for OS Functions (3/3)
Conclusion
Key Points of this Chapter
Questions
Exercises
Chapter 8: Real-time Operating Systems
Introduction8.1 Real-time Tasks8.1.1 Terms and Defintions8.1.2 Scheme of a Time Constrained Task Execution8.1.3 Types of Real-time Tasks
8.2 Real-time Systems
8.3 Types of Real-time Tasks8.3.1 Periodic Tasks8.3.2 Aperiodic Tasks8.3.3 Sporadic Tasks8.3.4 Preemptible/Non-preemptible Tasks
8.4 Real-time Operating Systems
8.5 Real-time Scheduling Algorithms
8.5.1 Off Time Scheduling (Pre-run-time Scheduling)8.5.2 On Line Scheduling
8.6 Rate Monotonic Algorithm
8.7 The Earliest Deadline First Algorithm
8.7.1 Disadvantages of EDF
8.8 Qualities of a Good RTOS
Conclusion
QuestionsExercises
Chapter 9: Programming in Embedded C
Introduction9.1 Embedded C9.1.1 The Header File
9.1.2 Serial Communication
9.2 PIC Programming Using MPLAB
Conclusion
Key Points of this ChapterQuestions
Exercises
Part III: Popular Microcontrollers Used in Embedded Systems
Chapter 10: ARM—The World’s Most Popular 32-bit Embedded Processor (Part I – Architecture and Assembly Language Programming)
Introduction10.1 History of the ARM Processor10.1.1 The ARM Core10.1.2 The ARM Microcontroller10.1.3 RISC vs CISC10.1.4 Advanced Features
10.1.5 Architecture Versions
10.1.6 ARM CORTEX10.1.7 The Features of ARM Which Makes it ‘Special’
10.2 ARM Architecture
10.2.1 Instruction Set Architecture10.2.2 Operating Modes10.2.3 Register Set10.2.4 Mode Switching10.2.5 Conditional Flags
10.3 Interrupt Vector Table
10.4 Programming the ARM Processor
10.4.1 Programming—Assembly vs C10.5 ARM Assembly Language10.5.1 Data Types10.5.2 Data Alignment
10.5.3 Assembly Language Rules
10.6 ARM Instruction Set10.6.1 Data Processing Instructions10.6.2 Shift and Rotate10.6.3 Format of Shift and Rotate Instructions10.6.4 Combining the Operations of Move and Shift
10.7 Conditional Execution
10.8 Arithmetic Instructions
10.8.1 Addition and Subtraction
10.9 Logical Instructions
10.10 Compare Instructions
10.11 Multiplication
10.11.1 Multiply
10.11.2 Multiply and Accumulate
10.11.3 Long Multiply/Long Multiply and Accumulate10.12 Division
10.13 Starting Assembly Language Programming
10.13.1 The AREA Directive10.13.2 The ENTRY Directive
10.13.3 The END Directive
10.14 General Structure of an Assembly Language Line10.14.1 Directives for Defining Data
10.14.2 The EQU Directive
10.14.3 Constants Allowed10.14.4 The RN Directive10.15 Writing Assembly Programs
10.16 Branch Instructions
10.16.1 Subroutines/Procedures
10.17 Loading Constants
10.17.1 Generating a 32-bit Constant Using Rotation10.17.2 Literal Pools
10.18 Load and Store Instructions (1/2)
10.18.1 Bytes, Half Words and Words10.18.2 Loading Signed Numbers10.18.3 Indexed Addressing Modes
10.18 Load and Store Instructions (2/2)
10.19 Readonly and Read/Write Memory
10.20 Multiple Register Load and Store (1/2)
10.20.1 The LDM Instruction10.20.2 The STM instruction10.20.3 Stack10.20.4 Stacks and Subroutines/Procedures
10.20 Multiple Register Load and Store (2/2)
Conclusion
Key Points of this ChapterQuestions
Exercises
Chapter 11: ARM—The World’s Most Popular 32-bit Embedded Processor (Part II – Peripheral Programming of ARM MCU Using C)
Introduction
11.1 Block Diagram
11.2 Features of the LPC 214x Family
11.2.1 Memory11.2.2 Memory Map11.2.3 System Functions11.2.4 Internal Buses11.2.5 Memory Accelerator Module
11.3 Peripherals (1/6)
11.3.1 GPIO (General Purpose I/O)
11.3 Peripherals (2/6)
11.3.2 The Timer Unit
11.3 Peripherals (3/6)
11.3.3 Timer 0 in the Interupt Mode
11.3 Peripherals (4/6)
11.3.4 The Pulse Width Modulation Unit
11.3 Peripherals (5/6)
11.3.5 The UART
11.3 Peripherals (6/6)
11.3.6 The SSP Unit
11.4 ARM 911.5 ARM Cortex-M3
Conclusion
Key Points of this Chapter
Questions
Exercises
Chapter 12: Cypress’s PSoC: A Different Kind of MCU
Introduction
12.1 How to get a PSoC Development Kit
12.1.1 Development Kit12.1.2 History and Applications of PSoC12.1.3 What is Different About PSoC
12.2 The PSoC Family
12.2.1 Comparing PSoC3 and 512.2.2 Focus of the Chapter
12.3 PSoC1
12.3.1 The CY8C29xxx Series12.3.2 Pin Designations
12.4 The Internal Architecture of PSoC (1/2)
12.4.1 The PSoC Core12.4.2 The CPU Core (M8C)12.4.3 Memory12.4.4 Clock Sources12.4.5 The PSoC Designer
12.4 The Internal Architecture of PSoC (2/2)
12.4.6 General Purpose I/O (GPIO)
12.5 The Digital Sub System (1/2)12.5.1 Clock Input12.5.2 Interconnection Structure—Input
12.5 The Digital Sub System (2/2)
12.5.3 Interconnection Structure—Output
12.6 GPIO Pins
12.6.1 Drive Modes
12.6.2 Using the Drive Options
12.7 Digital Applications Using PSoC (1/2)12.7.1 API Function Naming Conventions12.7.2 The LED User Module12.7.3 The PWM (Pulse Width Modulation) Modules
12.7 Digital Applications Using PSoC (2/2)
12.7.4 Implement an LCD Display Design
12.8 The Analog Section (1/2)
12.8.1 Switched Capacitor Circuits12.8.2 SC and CT Blocks in PSoC12.8.3 Interconnects of the Analog Section
12.8 The Analog Section (2/2)
12.8.4 Internal Voltage References12.8.5 Programmable Gain Amplifier (PGA)12.8.6 Implementation of an ADC
12.9 System Resources
12.10 PSoC3 and PSoC5
12.10.1 PSoC312.10.2 PSoC512.10.3 Peripherals
Conclusion
Key Points of this Chapter
Questions
Exercises
Chapter 13: The 8051 Microcontroller: The Programmer’s Perspective
Introduction13.1 History and Family Details of 8051
13.1.1 Other Members of the Family
13.1.2 Learning the Features of 805113.2 8051: The Programmer’s Perspective13.2.1 Eight-bit Registers of 805113.2.2 Internal Memory13.2.3 Sixteen-bit Registers
13.2.4 Ports
13.3 Assembly Language Programming (1/2)13.3.1 Modes of Addressing
13.3 Assembly Language Programming (2/2)
13.4 Internal RAM
13.5 The 8051 Stack
13.5.1 The Push Operation13.5.2 The pop operation
13.6 Processor Status Word (PSW)
13.7 Assembler Directives
13.8 Storing Data in Code Memory (ROM)
13.9 The Instruction Set of 8051 (1/3)
13.9.1 Data Transfer Instructions13.9.2 Bit Manipulation Instructions13.9.3 Branch Instructions
13.9 The Instruction Set of 8051 (2/3)
13.9.4 Arithmetic Instructions
13.9 The Instruction Set of 8051 (3/3)
13.10 Port Programming (1/2)
13.10.1 Port Instructions13.10.2 Logical Instructions13.10.3 Complement Instruction13.10.4 Rotate Instructions
13.10 Port Programming (2/2)
13.11 Subroutines (Procedures)
13.11.1 LCALL13.11.2 ACALL
13.12 Delay Loops
13.12.1 Calculating Delay13.12.2 Using NOP
Key Points of this Chapter
Questions
Exercises
Chapter 14: Programming the Peripherals of 8051
Introduction14.1 Pin Configuration of 805114.1.1 The Crystal14.1.2 Power on Reset (POR)14.1.3 Port Pins
14.1.4 Pins for External Memory Interfacing
14.2 Programming the Internal Peripherals
14.3 Timers of 8051 (1/2)
14.3.1 Interval Timer14.3.2 Timer Programming14.3.3 The Timer Mode Register (TMOD)14.3.4 Clock Source for the Timer14.3.5 Steps in Programming an Interval Timer14.3.6 Writing the Mode Control Word14.3.7 Mode 1 Programming
14.3 Timers of 8051 (2/2)
14.3.8 Mode 2 Programming
14.4 Counter Programming
14.4.1 Measuring an Unknown Frequency14.4.2 Event Counting
14.5 Interrupts of 8051 (1/2)
14.5.1 Enabling Interrupts14.5.2 Using Timers in the Interrupt Mode14.5.3 Steps in Using Timer 0 in the Interrupt-driven Mode
14.5 Interrupts of 8051 (2/2)
14.5.4 External Hardware Interrupts14.5.5 Edge Triggering of the External Interrupts
14.6 Serial Communication (1/2)
14.6.1 Serial Transmission14.6.2 Serial Reception14.6.3 RS 232C14.6.4 Baud Rates14.6.5 Registers in the UART of 805114.6.6 Modes
14.6 Serial Communication (2/2)
14.6.7 Serial Reception
Conclusion
Key Points of this Chapter
Questions
Exercises
Chapter 15: DSP Processors
Introduction
15.1 The Application Scenario
15.1.1 List of Applications15.1.2 Embedded Devices and DSP
15.1.3 DSP Processors
15.1.4 Manufacturers of Digital Signal Processors15.2 General Features of Digital Signal Processors (1/3)15.2.1 Fast MAC Units15.2.2 Specialized Instructions15.2.3 Efficient Memory Accessing15.2.4 DMA for Input Data15.2.5 Circular Buffers15.2.6 Zero-overhead Looping15.2.7 Multiple Execution Units15.2.8 Address Generation Units
15.2 General Features of Digital Signal Processors (2/3)
15.2.9 Data Format15.2.10 Two Level Cache15.2.11 Programming Languages15.2.12 Real-time Operating Systems
15.2 General Features of Digital Signal Processors (3/3)
15.2.13 Power Dissipation15.2.14 Streamlined I/O and Specialized DSP Peripherals15.2.15 Parallelism in the Processor Architecture
15.3 SIMD Techniques (1/2)
15.3.1 The BlackFin Fixed Point Processor15.3.2 Block Diagram15.3.3 Instruction Set15.3.4 System Development Using BlackFin15.3.5 Dual Core BlackFin15.3.6 Evaluation Boards
15.3 SIMD Techniques (2/2)
15.3.7 Features of BF-21535
15.4 The SHARC Floating Point Processor
15.4.1 Common Architectural Features of SHARC15.4.2 The Tiger SHARC15.4.3 The Architecture of Tiger SHARC
15.5 DSP Processors of Texas Instruments (TI)
15.6 OMAP (Open Multimedia Applications Platform)
Conclusion
Key Points of this Chapter
Questions
Exercises
Part IV: Design and Performance Aspects
Chapter 16: Automated Design of Digital ICs
16.1 History of Integrated Circuit (IC) Design16.2 Types of Digital ICs16.2.1 Standard Products16.2.2 ASIC (Application Specifi c Integrated Circuit)16.2.3 Programmable Devices
16.3 ASIC Design
16.3.1 Hardware Description Languages16.3.2 Architectural Models16.3.3 Simulation16.3.4 Synthesis16.3.5 Front End Design Steps
16.3.6 Back-end Design Steps
16.4 ASIC Design: The Complete Sequence
Key Points of this Chapter
QuestionsExercises
Chapter 17: Hardware Software Co–design and Embedded Product Development Lifecycle Management
Introduction
17.1 Hardware Software Co-design
17.1.1 Steps in Co-design
17.1.2 Co-simulation and Co-synthesis
17.2 Modelling of Systems17.2.1 Data Flow Diagram17.2.2 Concurrent Processes17.2.3 Finite State Machines
Conclusion
17.3 Embedded Product Development Lifecycle Management17.3.1 Embedded Product Development17.3.2 Phases of the Design and Development of an Embedded Product
17.4 Lifecycle Models
17.4.1 The Waterfall Model17.4.2 The V Model17.4.3 The Iterative Model
Conclusion
Key Points of this Chapter
QuestionsExercises
Chapter 18: Embedded Design: A Systems Perspective
Introduction
18.1 A Typical Example
18.2 Product Design
18.2.1 The Concept of ‘Need’18.2.2 Requirements18.2.3 User’s Perspective18.2.4 User Research18.2.5 Feasibility Study18.2.6 Specifications
18.3 The Design Process (1/4)
18.3.1 The Starting Point18.3.2 Ergonomic Design
18.3 The Design Process (2/4)
18.3.3 Mechanical and Interface Design18.3.4 Software Design18.3.5 Hardware Design18.3.6 Schematic Design18.3.7 PCB Layout
18.3 The Design Process (3/4)
18.3.8 PCB Manufacturing and Assembly
18.3 The Design Process (4/4)
18.4 Testing
18.4.1 Design for Testabiliy (DFT)18.4.2 Levels of Testing
18.4.3 Reliability and ‘Standards’ Testing
18.4.4 Field Trials18.4.5 Signature Testing18.5 Bulk Manufacturing
18.5.1 Manufacturing Tests
18.5.2 Yield18.5.3 Product packing/DeliveryConclusion
Key Points of this Chapter
Questions
Exercises
Part V: Projects
Chapter 19: Academic Projects
Introduction19.1 Project No: 119.1.1 Introduction19.1.2 Robots and Vision19.1.3 Aim of the Project19.1.4 Problem Specification19.1.5 System Description19.1.6 Image (Video) Capture19.1.7 Image Analysis19.1.8 The Matrix19.1.9 Image Processing Techniques19.1.10 Ball Following Robot19.1.11 Signboard Guided Autonomous Robot
19.1.12 RS 232 Serial Communication
19.1.13 MMC/SD19.1.14 Angström OS19.1.15 Setting Up the Operating System19.1.16 Hardware19.1.17 Vision Guided Robot Algorithm
19.1.18 Implementation of the Robots
19.1.19 Signboard Guided Autonomous Robot19.1.20 Results
19.2 Project No: 2 (1/2)
19.2.1 Introduction19.2.2 The Microcontroller19.2.3 The Interfaces Required19.2.4 Memory Unit19.2.5 GPIO Settings (SSP/SPI1 Interface Settings)19.2.6 Basic SD Commands19.2.7 The Audio Codec19.2.8 The SPI0 Interface Settings19.2.9 Test Mode19.2.10 The 16 2 LCD Display
19.2 Project No: 2 (2/2)
19.2.11 Push Buttons19.2.12 Algorithm19.2.13 Results
19.3 Project No: 3 (1/2)
19.3.1 Introduction19.3.2 Problem Statement19.3.3 The Solution19.3.4 Overview of the Project19.3.5 Implementation
19.3 Project No: 3 (2/2)
19.3.6 Using the PIC MCU19.3.7 Setting Up GPS and GSM19.3.8 Observations and Conclusions
19.3.9 Future Scope
ConclusionKey Points of this ChapterQuestions
Exercises
Appendix A
Appendix B (1/2)
Appendix B (2/2)
Appendix C (1/4)
Appendix C (2/4)
Appendix C (3/4)
Appendix C (4/4)
Appendix D (1/3)
Appendix D (2/3)
Appendix D (3/3)
Bibliography
Index (1/4)
Index (2/4)
Index (3/4)
Index (4/4)

Content preview from Embedded Systems: An Integrated Approach by Pearson

BUSES AND PROTOCOLS 187

5.3.5.3 | The OSI Model

As Figure 5.28 shows, the Ethernet protocol is associated with only the data link and

physical layers of the OSI model.  e physical payer transforms data into bits that are

sent across the physical media.  e data link layer determines access to the network

media in terms of frames. Its sub-layer Media Access Control (MAC) is responsible for

physical addressing.  e TCP/IP (Transmission Control Protocol/Internet Protocol) on

Ethernet takes care of all the seven layers.

5.3.5.4 | Network Topology

 e computers in a LAN network may be connected in the bus or star topology.

Bus In a bus topolog ...

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Embedded Systems: An Integrated Approach by Pearson

by Lyla B Das

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