7 Equalization and Multilevel Modulation for Multi-Gbps Chip-to-Chip Links
Anthony Chan Carusone
CONTENTS
7.2.2 Serial Links over Backplanes
7.3.1 Linear Two-Port Networks
7.1 INTRODUCTION
To avoid becoming a bottleneck in large electronic systems, the bit rates that must be communicated over chip-to-chip communication links ...
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