Intel Threading Building Blocks

Memory Consistency and Fences

A processor may reorder memory reads and writes so they occur in an order that is inconsistent with the original program. Memory consistency is a term used to describe how inconsistent the processor’s actual memory accessing can be relative to the original program. Obviously, two accesses to a single location need to happen in an order which preserves the intent of the original program. It is not okay to reorder a read of a variable that occurs after a write of the same variable. What is less clear is whether the order of reads and writes of different variables (different addresses) matters. In a multithreaded environment, it may matter a great deal how reads and writes are ordered because multiple threads can view the state of memory. The stronger memory consistency is, the less challenging it is for programmers, but the more limiting it is for hardware efficiency.

Some processor architectures, such as the Intel Itanium, IBM POWER and PowerPC, and Alpha processors, have weak memory consistency, in which memory operations on different addresses may be reordered by the hardware for the sake of efficiency. For Sun SPARC processors, the ordering is different under Solaris (which uses total-store order or TSO) and Linux (which uses relaxed-memory order or RMO). Therefore, Sun SPARC has weak memory consistency under Linux but not under Solaris.

The subject is complex, and the interested reader should consult other works on the subject. If you are programming ...