The Definitive Guide to the ARM Cortex-M0

A

AAPCS

55 , 152–4 , 288–9 , 304 , 331

see alsoEABI

definition

55

abort

407–10

ADC (add with carry)

75 , 89 , 321 , 427–9 , 430

ADCS

118 , 441

ADD

75 , 79–80 , 87–9 , 107–13 , 115–6 , 291 , 441

see alsoarithmetic operations

instruction set summary

441

ADDS

79–81 , 88 , 107–15 , 118 , 120–2 , 167–8 , 289 , 302–4 , 306–7 , 372 , 441

see alsoarithmetic operations

instruction set summary

441

ADR

75 , 89 , 441

see alsoarithmetic operations

instruction set summary

441

Advanced RISC Machine Ltd

3–4

see alsoARM

AHB LITE bus interface unit

14 , 65 , 125–39 , 321

see alsomemory… ; peripherals ; system bus

AIRCR

seeapplication interrupt and reset control register

ALIGN

77–8 , 112–3 , 165–8 , 294–8 , 303–4

ALU flags

13–24 , 28–31 , 78–9

see alsoAPSR register

concepts

28–31 , 78–9

example results ...