The System Designer's Guide to VHDL-AMS

appendix B

The Predefined Package Standard

The predefined types, subtypes and functions of VHDL-AMS are defined in a package called standard¹, stored in the library std. Each design unit in a design is automatically preceded by the following context clause:

library std, work; use std.standard.all;

so the predefined items are directly visible in the design. The package standard is listed here. The comments indicate which operators are implicitly defined for each explicitly defined type. These operators are also automatically made visible in design units. The types universal_integer and universal_real are anonymous types. They cannot be referred to explicitly.

¹From IEEE Standard 1076-2001. Copyright 2001 IEEE. All rights reserved.