Digital Arithmetic

450 c. ~i; ;~ p ~!~' ~i ~ ~ Floating-Point Representation, Algorithms, and Implementations

m W

t m

RIGHT

SHIFTER

t

3m+2

m+2

tm

mby m

MULTIPLIER

INCREMENTER '~ CSA+ADDER

•/m+

2 .~2m

To realign/normalize

FIGURE 8.22

Implementation of MAF adder.

Adder output 1~ m+2 ~l~ 2m ~l

Before shift 0000000000000000001.xxxxxxxxxxxxxxxxxxx

After shift 1.xxxxxxxxxxxxLGRT

F I G U R E 8.23

Left shifting of the adder output.

In floating-point addition the delay of the rounding is reduced by performing it

together with the addition and before the normalization. In the MAF case, this

delay reduction is difficult because, at the adder output, the ...