design of an SRT divider. Nannarelli and Lang (1998b) present power-delay
trade-offs in the design of digit recurrence dividers. The low-power design of
division and square root is the subject of a doctoral dissertation (Nannarelli 1999).
Verification
Formal verification of implementations of the SRT division is considered in
Bryant (1996), Clarke et al. (1999), and Ruess et al. (1999).
Delay and Area Bounds
Theoretical aspects of time and size complexity of the division operation is
considered in Beame et al. (1986), where the bounds on the depth of circuits
are developed. Optimal size of integer ...
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