September 2003
Intermediate to advanced
709 pages
26h 51m
English
Content preview from Digital Arithmetic
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Sequential Multiplication with Recoding
187
Cycle
Stage 1
Stage 2
Stage 3
CPA
0
LOAD X
LOAD Y
0
0
0
zo
0
0
Zl
Xzo
0
Z2
Xzl
PS[1]
SC[I]
z3
Xz2
PS[2]
sc[2]
F I G U R E 4.4
Timing diagram.
Z4
Xz3
PS[3]
sc[3]
m+l
XZm_l
PS[m - 11
SC[m - 11
m+2
PS[m]
SC[m]
Final product
by another bit because the multiple is signed (in two's complement representa-
tion); finally it is necessary to extend one more bit to accommodate the range of
the result of the addition.
The number of iterations is equal to the number of digits of the recoded
multiplier, that is, m = [(n + 1)/2]. The execution is illustrated in the timing
diagram shown in Figure ...
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