ESD: Design and Synthesis

About the Author

Dr Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge (ESD) for “Contributions in ESD Protection in CMOS, Silicon On Insulator and Silicon Germanium Technology.” He received his B.S. in Engineering Science from the University of Buffalo (1979); a first M.S. EE (1981) from Massachusetts Institute of Technology (MIT); a second EE Degree (Engineer Degree) from MIT; an M.S. Engineering Physics (1986) and a Ph.D. in electrical engineering (EE) (1991) from the University of Vermont under IBM's Resident Study Fellow program.

He was a member of the IBM development team for 25 years, working on semiconductor device physics, device design, and reliability (e.g., soft error rate (SER), hot electrons, leakage mechanisms, latchup, and ESD). Steve Voldman has been involved in latchup technology development for 27 years. He worked on both technology and with-product development in bipolar SRAM, CMOS DRAM, CMOS logic, silicon on insulator (SOI), BiCMOS, silicon germanium (SiGe), RF CMOS, RF SOI, smart power, and image processing technologies. In 2008 he was a member of the Qimonda DRAM development team, working on 70, 58, and 48 nm CMOS technology. In 2008 he initiated a limited liability corporation (LLC), and worked at headquarters in Hsinchu, Taiwan for Taiwan Semiconductor Manufacturing Corportion (TSMC) as part of the 45 nm ESD and latchup development team. He is presently a Senior Principal Engineer working for the Intersil Corporation on ...