ESD: Design and Synthesis

Acknowledgments

In the area of ESD and latchup design, I would like to acknowledge the years of support from the SEMATECH, the ESD Association, the IEEE, and the JEDEC organizations. I would like to thank the IBM Corporation, Qimonda, Taiwan Semiconductor Manufacturing Corporation (TSMC), and the Intersil Corporation. This text comes from 30 years of working with bipolar memory, DRAM memory, SRAM, NVRAMs, microprocessors, ASICs, mixed-voltage, mixed-signal, RF, and power applications. I was fortunate to work in a wide number of technology teams, and with a wide breadth of customers. I was very fortunate to work in bipolar memory, CMOS DRAM, CMOS logic, ASICs, silicon on insulator (SOI), and silicon germanium (SiGe) from 1 μm to 45 nm technologies. I was very fortunate to be a member of talented technology and design teams that were innovative, intelligent, and inventive. This provided the opportunity to explore experimental concepts, and try new ideas in ESD design in applications and products.

I would like to thank the institutions that allowed me to teach and lecture at conferences, symposiums, industry, and universities; this gave me the motivation to develop the texts. I would like to thank faculty at the following universities: MIT, Stanford University, University of Central Florida (UCF), University Illinois Urbana-Champaign (UIUC), University of California Riverside (UCR), University of Buffalo, National Chiao Tung University (NCTU), Tsin Hua University, National Technical ...