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Essentials of Computer Organization and Architecture, 5th Edition

by Linda Null, Julia Lobur

March 2018

Beginner

744 pages

26h 5m

English

Jones & Bartlett Learning

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1.1 Overview
1.2.1 The Main Components of a Computer1.2.2 System Components1.2.3 Classification of Computing Devices

1.5.1 Generation Zero: Mechanical Calculating Machines (1642–1945)1.5.2 The First Generation: Vacuum Tube Computers (1945–1953)1.5.3 The Second Generation: Transistorized Computers (1954–1965)1.5.4 The Third Generation: Integrated Circuit Computers (1965–1980)1.5.5 The Fourth Generation: VLSI Computers (1980–????)1.5.6 Moore’s Law
2.1 Introduction
2.3.1 Converting Unsigned Whole Numbers2.3.2 Converting Fractions2.3.3 Converting Between Power-of-Two Radices
2.4.1 Signed Magnitude2.4.2 Complement Systems2.4.3 Excess-M Representation for Signed Numbers2.4.4 Unsigned Versus Signed Numbers2.4.5 Computers, Arithmetic, and Booth’s Algorithm2.4.6 Carry Versus Overflow2.4.7 Binary Multiplication and Division Using Shifting
2.5.1 A Simple Model2.5.2 Floating-Point Arithmetic2.5.3 Floating-Point Errors2.5.4 The IEEE-754 Floating-Point Standard2.5.5 Range, Precision, and Accuracy2.5.6 Additional Problems with Floating-Point Numbers
2.6.1 Binary-Coded Decimal2.6.2 EBCDIC2.6.3 ASCII2.6.4 Unicode
2.7.1 Cyclic Redundancy Check2.7.2 Hamming Codes2.7.3 Reed-Solomon
3.1 Introduction
3.2.1 Boolean Expressions3.2.2 Boolean Identities3.2.3 Simplification of Boolean Expressions3.2.4 Complements3.2.5 Representing Boolean Functions
3.3.1 Symbols for Logic Gates3.3.2 Universal Gates3.3.3 Multiple Input Gates
3.4.1 Introduction3.4.2 Description of Kmaps and Terminology3.4.3 Kmap Simplification for Two Variables3.4.4 Kmap Simplification for Three Variables3.4.5 Kmap Simplification for Four Variables3.4.6 Don’t Care Conditions3.4.7 Summary
3.5.1 Digital Circuits and Their Relationship to Boolean Algebra3.5.2 Integrated Circuits3.5.3 Putting It All Together: From Problem Description to Circuit
3.6.1 Basic Concepts3.6.2 Examples of Typical Combinational Circuits
3.7.1 Basic Concepts3.7.2 Clocks3.7.3 Flip-Flops3.7.4 Finite-State Machines3.7.5 Examples of Sequential Circuits3.7.6 An Application of Sequential Logic: Convolutional Coding and Viterbi Detection
4.1 Introduction
4.2.1 The Registers4.2.2 The ALU4.2.3 The Control Unit
4.8.1 The Architecture4.8.2 Registers and Buses4.8.3 Instruction Set Architecture4.8.4 Register Transfer Notation
4.9.1 The Fetch–Decode–Execute Cycle4.9.2 Interrupts and the Instruction Cycle4.9.3 MARIE’s I/O
4.11.1 What Do Assemblers Do?4.11.2 Why Use Assembly Language?
4.13.1 Machine Control4.13.2 Hardwired Control4.13.3 Microprogrammed Control
4.14.1 Intel Architectures4.14.2 MIPS Architectures
5.1 Introduction
5.2.1 Design Decisions for Instruction Sets5.2.2 Little Versus Big Endian5.2.3 Internal Storage in the CPU: Stacks Versus Registers5.2.4 Number of Operands and Instruction Length5.2.5 Expanding Opcodes
5.3.1 Data Movement5.3.2 Arithmetic Operations5.3.3 Boolean Logic Instructions5.3.4 Bit Manipulation Instructions5.3.5 Input/Output Instructions5.3.6 Instructions for Transfer of Control5.3.7 Special-Purpose Instructions5.3.8 Instruction Set Orthogonality
5.4.1 Data Types5.4.2 Address Modes
5.6.1 Intel5.6.2 MIPS5.6.3 Java Virtual Machine5.6.4 ARM
6.1 Introduction
6.3.1 Locality of Reference
6.4.1 Cache Mapping Schemes6.4.2 Replacement Policies6.4.3 Effective Access Time and Hit Ratio6.4.4 When Does Caching Break Down?6.4.5 Cache Write Policies6.4.6 Instruction and Data Caches6.4.7 Levels of Cache
6.5.1 Paging6.5.2 Effective Access Time Using Paging6.5.3 Putting It All Together: Using Cache, TLBs, and Paging6.5.4 Advantages and Disadvantages of Paging and Virtual Memory6.5.5 Segmentation6.5.6 Paging Combined with Segmentation
7.1 Introduction
7.4.1 I/O Control Methods7.4.2 Character I/O Versus Block I/O7.4.3 I/O Bus Operation7.4.4 I/O Buses and Interfaces
7.5.1 Parallel Data Transmission7.5.2 Serial Data Transmission
7.6.1 Rigid Disk Drives7.6.2 Solid State Drives
7.7.1 CD-ROM7.7.2 DVD7.7.3 Blue-Violet Laser Discs7.7.4 Optical Disk Recording Methods
7.8.1 LTO: Linear Tape Open
7.9.1 RAID Level 07.9.2 RAID Level 17.9.3 RAID Level 27.9.4 RAID Level 37.9.5 RAID Level 47.9.6 RAID Level 57.9.7 RAID Level 67.9.8 RAID DP7.9.9 Hybrid RAID Systems
8.1 Introduction
8.2.1 Operating Systems History8.2.2 Operating System Design8.2.3 Operating System Services
8.3.1 Virtual Machines8.3.2 Subsystems and Partitions8.3.3 Protected Environments and the Evolution of Systems Architectures
8.4.1 Assemblers and Assembly8.4.2 Link Editors8.4.3 Dynamic Link Libraries8.4.4 Compilers8.4.5 Interpreters
9.1 Introduction
9.4.1 Superscalar and VLIW9.4.2 Vector Processors9.4.3 Interconnection Networks9.4.4 Shared Memory Multiprocessors9.4.5 Distributed Computing
9.5.1 Dataflow Computing9.5.2 Neural Networks9.5.3 Systolic Arrays
10.1 Introduction
10.2.1 Off-the-Shelf Embedded System Hardware10.2.2 Configurable Hardware10.2.3 Custom-Designed Embedded Hardware
10.3.1 Embedded Systems Memory Organization10.3.2 Embedded Operating Systems10.3.3 Embedded Systems Software Development
11.1 Introduction
11.3.1 What the Means Mean11.3.2 The Statistics and Semantics
11.4.1 Clock Rate, MIPS, and FLOPS11.4.2 Synthetic Benchmarks: Whetstone, Linpack, and Dhrystone11.4.3 Standard Performance Evaluation Corporation Benchmarks11.4.4 Transaction Processing Performance Council Benchmarks11.4.5 System Simulation
11.5.1 Branch Optimization11.5.2 Use of Good Algorithms and Simple Code
11.6.1 Understanding the Problem11.6.2 Physical Considerations11.6.3 Logical Considerations

Content preview from Essentials of Computer Organization and Architecture, 5th Edition

EXERCISES

1. What happens if an infinite loop includes a watchdog timer reset? Name one thing that can be done to guard against this.
◆2. In the sidebar concerning watchdog timer engineering decisions, we stated that rebooting an embedded system typically takes less time than rebooting a personal computer. Why do you think this is so?
3. a) Show how a two-input XOR gate can be implemented in the PAL shown below.
1. b) Show how a two-input NAND gate can be implemented in the PLA shown below.
4. Use the FPGA illustrated ...

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Publisher Resources

ISBN: 9781284123043