October 2016
Intermediate to advanced
454 pages
8h 40m
German
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13 Ausflug zu Verilog
In diesem Buch wird VHDL als Hardwarebeschreibungssprache verwendet. Dennoch folgt nun ein kurzer Abschnitt zu Verilog. Die wesentliche Motivation dafür ist, dass man als fortgeschrittener VHDL-Anwender in der Lage sein sollte, in Verilog vorliegende Module (die z.B. von »OpenCores.org« stammen) in eigene VHDL-Projekte einzubinden. Dazu muss man in der Hauptsache wissen, wie das Interface eines Verilog-Moduls aufgebaut ist und wie ein Verilog-Modul in ein VHDL-Projekt eingebunden wird.
13.1 Einstieg in Verilog
Als Einstieg in Verilog wird hier das Modul fpga_basic benutzt, das in diesem Buch (Anhang) bei der Vorstellung der diversen FPGA-Entwicklungsumgebungen verwendet wird.
Listing 13-1 zeigt die VHDL-Version, die jetzt ...
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