book

Integrated Power Devices and TCAD Simulation

by Yue Fu, Zhanming Li, Wai Tung Ng, Johnny K.O. Sin

December 2017

Intermediate to advanced

364 pages

11h 17m

English

CRC Press

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Cover Page
Title Page
Copyright Page
Contents
Preface
About the Authors
Chapter 1 Power Electronics, the Enabling Green Technology
1.1 Introduction to Power Electronics1.2 History of Power Electronics1.3 DC/DC Converters1.4 Linear Voltage Regulators1.5 Switched Capacitor DC/DC Converters (Charge Pumps)1.6 Switched Mode DC/DC Converters1.7 Comparison Between Linear Regulators, Charge Pumps, and Switched Regulators1.8 Topologies for Nonisolated DC/DC Switched Converters1.8.1 Buck Converter1.8.2 Boost Converter1.8.3 Buck–Boost Converter1.8.4 Ćuk Converter1.8.5 Additional Topics in Nonisolated Converters1.8.5.1 Nonideal Power Elements1.8.5.2 Synchronous Rectification1.8.5.3 Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM)1.8.5.4 Interleaving1.8.5.5 Ripples1.8.5.6 Comparison of Nonisolated Topologies1.9 Topologies for Isolated Switching Converters1.9.1 Flyback Converters1.9.2 Forward Converters1.9.3 Full-Bridge Converters1.9.4 Half-Bridge Converters1.9.5 Push–Pull Converters1.9.6 Additional Topics in Isolated DC/DC Converters1.9.6.1 Synchronous Rectification of Isolated DC/DC Converters1.9.6.2 Power MOSFET Parallel Body Diode Conduction1.9.6.3 Transformer Utilization1.9.6.4 Voltage Stress on the Active Power Transistor1.9.7 Comparison of Isolated DC/DC Converter Topologies1.10 Spice Circuit Simulation1.11 Power Management Systems for Battery-Powered Devices1.12 Summary
Chapter 2 Power Converters and Power Management ICs
2.1 Dynamic Voltage Scaling for Vlsi Power Management2.2 Integrated DC/DC Converters2.2.1 Segmented Output Stage2.2.2 Transient Suppression with an Auxiliary Stage2.3 Summary
Chapter 3 Semiconductor Industry and More than Moore
3.1 Semiconductor Industry3.2 History Of The Semiconductor Industry3.2.1 A Brief Timeline3.2.2 The Traitorous Eight3.2.3 Historical Road Map of the Semiconductor Industry3.3 Food Chain Pyramid of the Semiconductor Industry3.3.1 Level 1: Wafer and EDA Tools3.3.2 Level 2: Device Engineering3.3.3 Level 3: IC Design3.3.4 Level 4: Manufacturing, Packaging, and Testing3.3.5 Level 5: Systems and Software3.3.6 Level 6: Marketing and Sales3.4 Semiconductor Companies3.5 More than Moore
Chapter 4 Smart Power IC Technology
4.1 Smart Power IC Technology Basics4.2 Smart Power IC Technology: Historical Perspective4.3 Smart Power IC Technology: Industrial Perspective4.3.1 Engineering Groups of a Smart Rower IC Technology4.3.1.1 Process Integration4.3.1.2 TCAD Support4.3.1.3 Compact Modeling4.3.1.4 Device Design4.3.1.5 ESD Design4.3.1.6 Process Design Kit4.3.1.7 IC Design Group4.3.1.8 Reliability Group4.3.1.9 Packaging4.3.2 Smart Rower IC Technology Development Flow4.3.3 Planning Stage4.3.4 Process Integration and Device Design4.3.5 Layout, Tape-Out, Fabrication, and Test4.3.6 Reliability and Qualification4.3.7 Survey of Current Smart Power Technology4.4 Smart Power IC Technology: Technological Perspective4.4.1 Devices for Smart Power Technology4.4.2 Design Considerations for Smart Power IC Technology4.4.2.1 Power MOSFETs4.4.2.2 LIGBTs4.4.2.3 Analog Active Devices4.4.2.4 Resistors4.4.2.5 Capacitors4.4.2.6 Voltage and Frequency Trims4.4.2.7 Logic/Digital NMOS and PMOS4.4.2.8 System-Level Design and Fabrication Considerations4.4.3 Isolation Methods

Chapter 5 Introduction to TCAD Process Simulation
5.1 Overview5.2 Mesh Setup and Initialization5.3 Ion Implantation5.3.1 Analytical Models5.3.2 Multiple-Layer Implantation5.3.3 Monte Carlo Simulation5.4 Deposition5.5 Oxidation5.5.1 Dry Oxidation5.5.2 Wet Oxidation5.5.3 Oxidation Models5.5.3.1 Moving Boundaries5.5.3.2 2D Analytical Models5.5.3.3 Numerical Models5.5.3.4 LOCOS Growth Example5.6 Etching5.7 Diffusion5.7.1 Diffusion Mechanisms5.7.1.1 Direct Diffusion Mechanism5.7.1.2 Vacancy Mechanism5.7.1.3 Interstitials Mechanism5.7.2 Diffusion Models5.7.2.1 Fermi Diffusion Model5.7.2.2 Two-Dimensional Diffusion Model5.7.2.3 Fully Coupled Diffusion Model5.7.2.4 Steady-State Diffusion Model5.7.2.5 Oxide Enhanced (Retarded) Diffusion5.8 Segregation5.9 Process Simulator Models Calibration5.10 Introduction to 3D TCAD Process Simulation5.11 GPU Simulation
Chapter 6 Introduction to TCAD Device Simulation
6.1 Overview6.2 Basics About Device Simulation6.2.1 Drift-Diffusion Model6.2.2 Discretization6.2.3 Newton’s Method6.2.4 Initial Guess and Adaptive Bias Stepping6.2.5 Convergence Issues6.2.6 Boundary Conditions6.2.6.1 Ohmic Contact6.2.6.2 Schottky Contacts6.2.6.3 Neumann Boundaries6.2.6.4 Lumped Elements6.2.7 Transient Simulation6.2.8 Mesh Issues6.3 Physical Models6.3.1 Carrier Statistics6.3.2 Incomplete Ionization of Impurities6.3.3 Heavy Doping Effect6.3.4 SRH and Auger Recombination6.3.5 Avalanche Breakdown and Impact Ionization6.3.5.1 Avalanche Breakdown6.3.5.2 Impact Ionization Coefficients6.3.5.3 C hynoweth’s Law6.3.5.4 Baraff Model6.3.5.5 Fulop’s Approximation6.3.5.6 Okuto–Crowell Model6.3.5.7 Lackner Model6.3.5.8 Mean Free Path Model6.3.5.9 Multiplication Factor and Ionization Integral6.3.5.10 Critical Electric Field6.3.5.11 Analytical Breakdown Voltage6.3.5.12 Benchmark Comparison of Avalanche Breakdown Models6.3.6 Carrier Mobility6.3.6.1 Models Overview6.3.6.2 C onstant Mobility6.3.6.3 Two-Piece Mobility Model6.3.6.4 Canali or Beta Model6.3.6.5 Transferred Electron Model6.3.6.6 Poole–Frenkel Field Enhanced Mobility Model6.3.6.7 Impurity Dependence of the Low Field Mobility Model6.3.6.8 Intel’s Local Field Models6.3.6.9 Lombardi Model6.3.6.10 Comparison of Different Diffusion Models6.3.6.11 GaN Mobility Model (MTE Model)6.3.7 Thermal and Self-Heating6.3.7.1 Heat Flow and Temperature Distribution6.3.8 Bandgap Narrowing Effect6.4 AC Analysis6.4.1 Introduction6.4.2 Basic Formulas6.4.3 AC Analysis in TCAD6.5 Trap Model in TCAD Simulation6.5.1 Trap-Charge States6.5.2 Trap Dynamics6.6 Quantum Tunneling6.6.1 Importance of Quantum Tunneling for Power Devices6.6.2 Basic Theory of Tunneling for TCAD Simulation6.6.3 Introduction to Nonequilibrium Green’s Function for Tunneling6.7 Device Simulator Models Calibration
Chapter 7 Power IC Process Flow with TCAD Simulation
7.1 Overview7.2 A Mock-Up Power IC Process Flow7.2.1 Process Flow Steps7.2.2 Structure View of the Mock-Up Process Flow7.3 Smart Power IC Process Flow Simulation7.3.1 P+ Substrate7.3.2 N+ Buried Layer7.3.3 Epitaxial Layer Growth and Deep N Link7.3.4 High-Voltage Twin-Well7.3.5 P-Body Implant for n-LDMOS7.3.6 Active Area/Shallow Trench Isolation (STI)7.3.7 N-Well and P-Well7.3.8 Low-Voltage Twin Wells7.3.9 Thick Gate and Thin Gate Oxide7.3.10 Poly Gate7.3.11 NLDD and PLDD7.3.12 Sidewall Spacer7.3.13 NSD and PSD7.3.14 Back-End of the Line
Chapter 8 Integrated Power Semiconductor Devices with TCAD Simulation
8.1 PN Junction Diodes8.1.1 PN Junction Basics8.1.2 Lateral PN Junction Diode at Equilibrium8.1.3 Forward Conduction (On-State)8.1.4 Reverse Bias of a PN Junction Diode8.1.5 Lateral PN Junction Diode with NBL8.1.6 Breakdown Voltage Enhancement of the PN Junction Diode8.1.6.1 Basic Understanding of How to Improve Breakdown Voltage8.1.6.2 Different P-substrate Doping for the PN Junction Diode without NBL8.1.6.3 Breakdown Enhancement for Diode with NBL8.1.6.4 Reverse Leakage Current Path with Substrate Contact8.1.7 Reverse Recovery8.1.7.1 Basic Understanding of Diode Reverse Recovery8.1.7.2 D iode Reverse Recovery TCAD Simulation8.1.7.3 TCAD Simulations for Carrier Lifetime Engineering8.1.8 Schottky Diode8.1.9 Zener Diode8.1.10 Small Signal Model for FN Junction Diode8.2 Bipolar Junction Transistors8.2.1 Basic Operation of NPN BJTs8.2.1.1 Simulation Structure8.2.1.2 Collector and Base Current8.2.1.3 Transistor Gain and Gummel Plot8.2.2 NPN BJT Breakdown8.2.2.1 BVCBO8.2.2.2 BVEBO8.2.2.3 BVCEO8.2.2.4 BVCES8.2.2.5 Comparison of the Four Types of NPN Breakdown8.2.3 BJT I-V Family of Curves8.2.4 Kirk Effect8.2.5 BJT Thermal Runaway and Second Breakdown Simulation8.2.6 BJT Small Signal Model and Cutoff Frequency Simulation8.2.6.1 Cutoff Frequency8.3 LDMOS8.3.1 Breakdown Voltage Improvement8.3.1.1 Basic LDMCS structure with N-Type Epitaxial Layer (LDMCS I)8.3.1.2 LDMOS with Shielding Plate (LDMOS II)8.3.1.3 LDMOS with STI in the Drain-Drift Region (LDMOS III)8.3.1.4 LDMOS with Both STI Oxide and Field Plate (LDMOS IV)8.3.1.5 LDMOS with RESURF from P-epi Layer (LDMOS V)8.3.1.6 LDMOS with P-epi RESURF and STI (LDMOS VI)8.3.1.7 LDMOS with Double RESURF (LDMOS VII)8.3.1.8 LDMOS Multiple RESURF (LDMOS VIII)8.3.1.9 comparison of 3D surface Plot of Electric Field8.3.2 Parasitic NPN BJTs in LDMOS8.3.3 LDMOS On-State Resistance8.3.3.1 Specific On-Resistance8.3.3.2 On-Resistance Contribution8.3.3.3 Comparison of Breakdown Voltage and On-Resistance8.3.4 LDMOS Threshold Voltage8.3.5 LDMOS with Radiation Hardening Design8.3.6 LDMOS I-V Family of Curves8.3.7 LDMOS Self-Heating8.3.8 LDMOS Parasitic Capacitances8.3.9 LDMOS Gate Charge8.3.10 LDMOS Unclamped Inductive Switching (UIS)8.3.11 Compact Models of LDMOS
Chapter 9 Integrated Power Semiconductor Devices with 3D TCAD Simulations
9.1 3D Device Layout Effect9.2 3D Simulation of Ligbt9.2.1 About LIGBT9.2.2 Segmented Anode LIGBT9.2.3 3D Process Simulation of Segmented Anode LIGBT9.2.4 3D Device Simulation of Segmented Anode LIGBT9.2.4.1 Forward Characteristic Simulation9.2.4.2 LIGBT Turnoff Transient Simulation9.2.4.3 Forward I-V Family of Curves Comparison with LDMOS9.3 Super Junction LDMOS9.3.1 Basic Concept9.3.1.1 How to Choose the Pillar Width WN9.3.1.2 About Dose Balance9.3.1.3 On-Resistance9.3.2 Super Junction LDMOS Structure9.3.3 3D Process Simulation of Super Junction LDMOS9.3.4 3D Device Simulation of Super Junction LDMOS9.3.5 3 D Simulation of a Standard LDMOS with the Same N-Drift Doping9.3.6 3D Simulation of a Standard LDMOS with Reduced N-Drift Doping9.3.7 Comparison of Super Junction LDMOS and Standard LDMOS9.4 Super Junction Power FinFET9.4.1 Process Flow of the Super Junction Power FinFET9.4.2 Measurement Results of Super Junction Power FinFET9.4.3 3D Simulation of Super Junction Power FinFET9.5 Large Interconnect Simulation9.5.1 3D Process Simulation of the Large Interconnect9.5.1.1 Substrate9.5.1.2 Contacts9.5.1.3 Metal19.5.1.4 Via19.5.1.5 Metal29.5.1.6 Via29.5.1.7 Metal39.5.2 3D Device Simulation of the Large Interconnect
Chapter 10 GaN Devices, an Introduction
10.1 Compound Materials Versus Silicon10.2 Substrate Materials for GaN Devices10.3 Polarization Properties Of III-Nitride Wurtzite10.3.1 Microscopic Dipoles and Polarization Vector10.3.2 Crystal Structure and Polarization10.3.3 Ideal c0/a0 Ratio for Zero Net Polarization10.3.3.1 Strain-Induced Polarization10.3.3.2 Empirical Approach to Modeling Polarization10.4 AlGaN/GaN Heterojunction10.4.1 Band Diagram Plots with a Fixed Al Mole Fraction10.4.2 Band Diagram Plots with a Fixed AlGaN Thickness10.4.3 AlGaN/GaN Structure with Doped AlGaN or GaN Layer.10.4.4 AlGaN/GaN Structure with Metal Contacts10.5 Traps in AlGaN/GaN Structure10.6 A Simple AlGaN/GaN HEMT10.6.1 Device Structure10.6.2 ID-VG Curves for GaN HEMT10.6.3 Summary10.7 GaN Power HEMT Example I10.7.1 Device Structure10.7.2 Impact Ionization Coefficient of GaN Material10.7.3 Breakdown Simulation of GaN HEMT10.8 GaN Power HEMT Example II10.9 Gate Leakage Simulation of GaN HEMT10.9.1 Device Structure10.9.2 Models and Simulation Setup10.9.3 Gate Leakage Simulation10.9.3.1 Pure TCAD Simulation10.9.3.2 TCAD Simulation with Slow Transient10.9.3.3 TCAD Simulation with Equivalent Circuits10.10 Market Prospect of Compound Semiconductors for Power Applications
Appendix A: Carrier Statistics
Appendix B: Process Simulation Source Code
Appendix C: Trap Dynamics and AC Analysis
Bibliography
Index

Content preview from Integrated Power Devices and TCAD Simulation

Index

Note: Page numbers ending in “e” refer to equations. Page numbers ending in “f” refer to figures. Page numbers ending in “t” refer to tables.

2DEG, 281, 287–301

3D device layout effect, 239–242

3D effects, 82–83, 239

3D integration, 49

3D TCAD simulations

3D device layout effect, 239–242

breakdown voltage, 268f, 272f

dose imbalanced structure, 258–260, 259f–261f

gate oxide, 246, 271, 296

impact ionization, 238, 266–267

implantation, 269–270

introduction to, 82–83

I-V curves, 248f, 255f

large interconnect simulation, 274–280, 275f–280f

layout structures, 240f

LDMOS, 240–244, 243f, 248–249, 255f, 256f, 266f, 268f, 270–276, 274f

LIGBT simulation, 242–254, 242f–247f, 246t–247t, 249f–255f

N/P structures, 254–260, 255e

on-resistance, 260–261 ...

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Integrated Power Devices and TCAD Simulation

by Yue Fu, Zhanming Li, Wai Tung Ng, Johnny K.O. Sin

Index

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