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Linux Device Drivers Development
book

Linux Device Drivers Development

by John Madieu
October 2017
Intermediate to advanced
586 pages
14h 8m
English
Packt Publishing
Content preview from Linux Device Drivers Development

CPU cache – memory caching

There are three cache memories on the modern CPU, ordered by size and access speed:

  • The L1 cache has the smallest amount of memory (often between 1K and 64K) and is directly accessible by the CPU in a single clock cycle, which makes it the fastest as well. Frequently used things are in L1 and remain in L1 until some other thing's usage becomes more frequent than the existing one and there is less space in L1. If so, it is moved to a bigger L2.
  • The L2 cache is the middle level, with a larger amount of memory (up to several megabytes) adjacent to the processor, which can be accessed in a small number of clock cycles. This applies when moving things from L2 to L3.
  • The L3 cache, even slower than L1 and L2, may be twice ...
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Publisher Resources

ISBN: 9781785280009Supplemental Content