The Maplin Electronic Circuits Handbook, 2nd Edition

146 LOGIC CIRCUITS

Table 6.10

J

κ

ßn

+

l

Comment

Present

Clear

e

0

0

Qn

No change

0

0

Indeterminate

0

1

0

Output cleared

0

1 1

1

0

1

Output set

1

0 0

1

1

On

Output changes

1

1

Enables clocked

state

operation

Data input

Figure

6.32 Timing

diagram

for

the one-bit data latch shown in

Figure 6.31

Clock

Q output

Q output

Time -

It is important to note that the CLEAR input of a 7473 bistable should

never be left to float into the logic 1 state. The CLEAR input should

always be pulled-up to logic 1 (using a shared pull-up resistor if necessary).

Failure to observe this precaution may result in spurious output states

(glitches).

Counters and shift register ...