The Maplin Electronic Circuits Handbook, 2nd Edition

150 LOGIC CIRCUITS

Data input

14

74LS04

^

Clock

Reset

Figure 6.38 Four-stage shift

register using J Κ bistables

Figure 6.39 Timing

diagram

for

the shift register shown in

Figure 6.38

CLOCK

K

Q

CLEAR

—το—

12

13

7473

10

J Q

CLOCK

Κ Ο

CLEAR

14

J Q

CLOCK

Κ Q

CLEAR

12

•+

5

V

13

ic

2

7473

10

J Q

CLOCK

K

Q

CLEAR

-0 V

Clock

ΠΠΠΠΠΠΠΠΠΠΠΠΠΠΠΠΠΓ

Time

Logic gate oscillators

Logic circuits often require the services of a locally generated clock signal.

Depending upon the characteristics required, various circuit configurations

are possible. The following checklist indicates the features of a clock signal

which may or may not be significant in any particula ...