Verilog Coding for Logic Synthesis

Index

A

addition operator 78, 79, 80

architectural 5, 10, 151, 181

arithmetic operator 79

asynchronous 51, 52, 128

B

bitwise operator 105, 106, 107, 108, 109

blocking xxiv, 54, 55, 60, 61, 62, 63, 64, 65

buf 32, 33, 34

bufif0 31, 32, 34

bufif1 32, 34

C

cmos 28, 29, 34

concatenation operator 69

conditional operator 68, 69, 127

control word register 151, 152, 153, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 170, 171, 172, 173, 175, 176, 178, 180, 216

D

division operator 78, 85, 86, 87, 92

E

equality operator 112, 113

F

fanout 48

G

gated clock 47, 48, 50

I

inference xxiv, 121

integer 18, 19, 67, 76, 80, 81, 84, 86, 92, 93, 102, 108, 114, 116, 119, 128, 129, 216, 293, 295, 297

L

logical operator 100, 101, 105, 107, 108, 115

M

modulus operator 78, 92

multiplication operator 78, 82, 85

N

naming convention xxiv, 41, 42

nand 33, 34

nmos 28, 34

non-blocking xxiv, 54, 55, 59, 60, 65

nor 33, 34

notif0 30, 31, 34

notif1 30, 34

O

P

pmos 28, 34

pulldown 29, 34

pullup 29, 34

R

rcmos 29, 34

real 17, 42, 151

reduction operator 115

relational operator 117, 118

rnmos 29, 34

rpmos 29, 34

rtran 30, 34

rtranif0 30, 34

rtranif1 30, 34

S

sensitivity list xxiv, 66, 67, 68

subtraction operator 78, 80, 81

supply0 22

supply1 22

synchronous 52, 53, 55, 60, 63, 64, 65

T

time 1, 10, 17, 19, 138, 155, 161, 167, 174, 191

timing loop xxiv, 53, 54

tran 30, 34

tranif0 30, 34

tranif1 30, 34

tri 22, 24

tri0 23, 25, 26

tri1 23, 24, 25

triand 23, 24, 25

trior 23, 24

trireg 23, 24, 25

U

UDP 34,